False Paths

  • Sridhar Gangadharan
  • Sanjay Churiwala


So far we saw how you can constrain your clocks and ports to specify the timing requirements for the design. However, even after setting these global requirements, designers would want to make certain exclusions for certain paths. This may be done to specify certain unique requirements on the paths or provide additional scope for leniency. Such constraints are referred to as timing exceptions. There are three kinds of timing exceptions:


False Paths Exclusion Time Rise Transition Active Clock Edge Output Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Sridhar Gangadharan
    • 1
  • Sanjay Churiwala
    • 2
  1. 1.Atrenta, Inc.San JoseUSA
  2. 2.XilinxHyderabadIndia

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