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The Promises and Limitations of 3-D Integration

  • Axel JantschEmail author
  • Matthew Grange
  • Dinesh Pamunuwa
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use ECE and ECD to study the limits of performance under different memory distribution constraints of various 2-D and 3-D topologies, in current and future technology nodes. Among other results, our model shows that in a 35 nm technology a 16 stack 3-D system can, as a theoretical upper limit, obtain 3.4 times the performance of a 2-D system (8.8 Tera OPS vs 2.6 TOPS) at 70% reduced frequency (2.1 vs 3.7 GHz) on 1/8 the total area (50 vs 400 mm2).

Keywords

Memory Access Centralize Memory Computation Unit Geometric Distance Technology Node 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Department of Electronic Systems School of Information and Communication TechnologyRoyal Institute of TechnologyKistaSweden

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