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Three-Dimensional Integration of Integrated Circuits—an Introduction

  • Chuan Seng TanEmail author
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Three-dimensional (3D) stacking of ultra-thin integrated circuits (ICs) is identified as an inevitable solution for future system miniaturization and functional diversification. 3D integration offers a long list of benefits in terms of system form factor, density scaling and multiplication, reduced interconnection latency and power consumption, bandwidth enhancement, and heterogeneous integration of disparate technologies. In this 3D implementation, thinned IC layers are seamlessly bonded with a reliable bonding medium and vertically interconnected with electrical through strata via (TSV). The objective of this chapter is to discuss performance enhancement as well as new integration capabilities brought about by 3D technology, enabling technology platforms, and potential applications made possible by 3D technology.

Keywords

Device Layer Wafer Bonding CMOS Image Sensor Electron Dispersion Spectroscopy Geometrical Scaling 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

The author is supported by funding from the Nanyang Technological University through an award of Nanyang Assistant Professorship, Defense Science and Technology Agency (DSTA, Singapore), Semiconductor Research Corporation (SRC, USA) through a subcontract from the Interconnect and Packaging Center at the Georgia Institute of Technology, and Defense Advanced Research Projects Agency (DARPA, USA). The author thanks Professor Rafael Reif of MIT for his constructive and valuable comments on the content of this chapter.

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.School of Electrical and Electronic EngineeringNanyang Technological UniversitySingaporeSingapore

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