I/O overhead and parallel VLSI architectures for lattice computations
In this paper we introduce input/output (I/O) overhead ψ as a complexity measure for VLSI implementations of two-dimensional lattice computations of the type arising in the simulation of physical systems. We show by pebbling arguments that ψ = Ω(n−1) when there are n2 processing elements available. If the results are required to be observed at every generation, and no on-chip storage is allowed, we show the lower bound is the constant 2. We then examine four VLSI architectures and show that one of them, the multi-generation sweep architecture, also has I/O overhead proportional to n−1. We compare the constants of proportionality between the lower bound and the architecture.
KeywordsInput/output complexity lattice computations cellular automata pebbling VLSI architectures
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