Mispredicted Path Cache Effects
- 79 Downloads
As superscalar pipelines become wider and deeper, the percentage of dynamic instructions fetched into the machine from the mispredicted path significantly increases. This paper discusses how a new cycle-accurate performance simulator is used to accurately measure mispredicted path effects on the cache hierarchy. Previously published results based on less accurate tools indicated that mispredicted path instructions have the serendipitous positive effect of doing memory prefetching. Our results show that while such prefetching does occur for some benchmarks, it does not occur consistently for all benchmarks. Furthermore the IPC impact varies widely among the benchmarks. SPECint95 benchmarks show IPC changes ranging from -8% to +12%.
KeywordsMemory Latency Instruction Cache Speculative Execution Branch Prediction Cache Hierarchy
- 1.C. Bechem, J. Combs, N. Utamaphethai, B. Black, R.D. Blanton, J.P. Shen. “An Integrated Functional Performance Simulator.” IEEE Micro, May-June 1999, pp 2–11.Google Scholar
- 2.B. Black and J.P. Shen. “Calibration of Microprocessor Performance Models.” COMPUTER, May 1998, pp. 59–65.Google Scholar
- 3.A. Cagney. PSIM User’s Guide. ftp://cambridge.cygnus.com/pub/psim/index.html August 1996.
- 4.K. Diefendorf and E. Silha. “The PowerPC User Instruction Set Architecture.” IEEE Micro, October 1994, pp. 30–41.Google Scholar
- 5.S. Jourdan, T. Hsing, J. Stark, and Y. Patt. “The Effects of Mispredicted-Path Execution on Branch Prediction Structures.” Conference on Parallel Architectures and Compilation Techniques (PACT), October 1996.Google Scholar
- 6.D. Lee, J-L. Baer, B. Calder, and D. Grunwald. “Instruction Cache Fetch Policies for Speculative Execution.” International Symposium on Computer Architecture, June 1995.Google Scholar
- 7.IBM Microelectronics Division, PowerPC 604 RISC Microprocessor User’s Manual 1994.Google Scholar
- 8.J. Pierce and T. Mudge. “The Effect of Speculative Execution of Cache Performance.” Proceedings of the International Parallel Processing Symposium, April 1994.Google Scholar
- 9.J. Pierce and T. Mudge. “Wrong Path Instruction Prefetching.” Technical Report, University of Michigan, 1994.Google Scholar
- 10.S. Song, M. Denman, and J. Chang, “The PowerPC 604 RISC Microprocessor.” IEEE Micro, October 1994, pp. 8–17.Google Scholar