An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors

  • Daniel A. Connors
  • David I. August
  • Kevin M. Crozier
  • andWen-mei W. Hwu
  • Jean-Michel Puiatti
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1685)


Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism (ILP) techniques that are traditionally used in high performance systems. Predicated execution, an important ILP technique, can be used to improve branch handling, reduce frequently mispredicted branches, and expose multiple execution paths to hardware resources. However, there is a major tradeoff in the design of the instruction set, the addition of a predicate operand for all instructions. We propose a new architecture framework for introducing predicated execution to embedded designs. Experimental results show a 10% performance improvement and a code reduction of 25% over a traditionally predicated architecture.


  1. [1]
    J. Davidson and R. Vaughan. The effect of instruction set complexity on program size and memory performance. In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, pages 60–64, October 1987.Google Scholar
  2. [2]
    S.A. Mahlke et al. Effective compiler support for predicated execution using the hyperblock. In Proceedings of the 25th International Symposium on Microarchitecture, pages 45–54, December 1992.Google Scholar
  3. [3]
    S.A. Mahlke et al. A comparison of full and partial predicated execution support for ILP processors. In Proceedings of the 22th International Symposium on Computer Architecture, pages 138–150, June 1995.Google Scholar
  4. [4]
    V. Kathail et al. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, Hewlett-Packard Laboratories, Palo Alto, CA, February 1994.Google Scholar
  5. [5]
    W.W. Hwu et al. The Superblock: An effective technique for VLIW and superscalar compilation. The Journal of Supercomputing, 7(1):229–248, January 1993.Google Scholar
  6. [6]
    R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31:1277–1284, 1996.Google Scholar
  7. [7]
    C. Lee and W. Mangione-Smith. Mediabench. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 330–335, December 1997.Google Scholar
  8. [8]
    MicroDesign Resources. Embedded Processor Forum, San Jose, CA, October 1998.Google Scholar
  9. [9]
    J.C. Park and M.S. Schlansker. On predicated execution. Technical Report HPL-91-58, Hewlett Packard Laboratories, Palo Alto, CA, May 1991.Google Scholar
  10. [10]
    D.N. Pnevmatikatos and G.S. Sohi. Guarded execution and branch prediction in dynamic ILP processors. In Proceedings of the 21st International Symposium on Computer Architecture, pages 120–129, April 1994.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Daniel A. Connors
    • 1
  • David I. August
    • 1
  • Kevin M. Crozier
    • 1
  • andWen-mei W. Hwu
    • 1
  • Jean-Michel Puiatti
    • 2
  1. 1.Department of Electrical and Computer Engineering, The Coordinated Science LaboratoryUniversity of IllinoisIllinoisUSA
  2. 2.Logic Systems Laboratory (DI-LSL)Swiss Federal Institute of Technology LausanneLausanneSwitzerland

Personalised recommendations