A Study of a Simultaneous Multithreaded Processor Implementation

  • Dominik Madoń
  • Eduardo Sánchez
  • Stefan Monnier
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1685)


This paper describes an approach to the implementation and the operation of a Simultaneous Multithreaded processor. We propose an architecture which integrates a software mechanism to handle contexts, a rapid communication system, as well as a locking system to ensure mutual exclusion. We explain how the architecture manages the running threads as well as the software interface visible to the programmer. Finally, we provide a few indications on the efficiency of such an architecture.


  1. [1]
    Douglas C. Burger and Todd M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.Google Scholar
  2. [2]
    S.J. Eggers, J. Emer, H.M. Levy, J.L. Lo, R. Stamm, and D.M. Tullsen. Simultaneous multithreading: A platform for next-generation processors. Technical Report TR-97-04-02, University of Washington, Department of Computer Science and Engineering, April 1997.Google Scholar
  3. [3]
    A. Farcy and O. Temam. Improving single-process performance with multithreaded processors. In Proceedings of the 1996 International Conference on Computing, pages 350–357, New York, May25-28 1996. ACM.Google Scholar
  4. [4]
    Manu Gulati and Nader Bagherzadeh. Performance study of a multithreaded superscalar microprocessor. In Proceedings of the Second International Symposium on High-Performance Computer Architecture, pages 291–301, San Jose, California, February 3-7, 1996. IEEE Computer Society TCCA.Google Scholar
  5. [5]
    Sébastien Hily and André Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading. Technical Report PI-1086, IRISA, University of Rennes 1, 35042 Rennes, France, February 1997.Google Scholar
  6. [6]
    Mat Loikkanen and Nader Bagherzadeh. Affine-grain multithreading superscalar architecture. In Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques (PACT’ 96), pages 163–168, Boston, Massachusetts, October 20–23, 1996. IEEE Computer Society Press.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Dominik Madoń
    • 1
  • Eduardo Sánchez
    • 1
  • Stefan Monnier
    • 2
  1. 1.Logic Systems LaboratorySwiss Federal Institute of Technology of LausanneLausanneSwitzerland
  2. 2.Computer Science Dept.Yale UniversityNew-HeavenUSA

Personalised recommendations