Vector ISA Extension for Sparse Matrix-Vector Multiplication

  • Stamatis Vassiliadis
  • Sorin Cotofana
  • Pyrrhos Stathis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1685)


In this paper we introduce a vector ISA extension to facilitate sparse matrix manipulation on vector processors (VPs). First we introduce a new Block Based Compressed Storage (BBCS) format for sparse matrix representation and a Block-wise Sparse Matrix-Vector Multiplication approach. Additionally, we propose two vector instructions, Multiple Inner Product and Accumulate (MIPA) and LoaD Section (LDS), specially tuned to increase the VP performance when executing sparse matrix-vector multiplications.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Stamatis Vassiliadis
    • 1
  • Sorin Cotofana
    • 1
  • Pyrrhos Stathis
    • 1
  1. 1.Electrical Engineering Dept.Delft University of TechnologyDelftThe Netherlands

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