Abstract
Delay and Area ceases the actual potential of the modern gadgets. Although, human has sophisticated devices around him yet yearns to save time and space. So, this paper centers on the highly efficient CORDIC algorithm, known for its low-cost implementation in DSP algorithms. In an effort, to improve the algorithm further in terms of area and speed, comparative analysis has been done by replacing Ripple carry adder with Parallel-Prefix adders, namely, Brent-Kung adder, Han-Carlson adder and Kogge-Stone Adder. The algorithm was designed in VHDL using XILINX ISE 14.7 design suite and implemented in XILINX Spartan 6e FPGA. Obviously, Parallel-Prefix adders have shown improved performance.
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Venkatesh, V., Yeswanth, B., Akhil, R., Jatoth, R.K. (2020). An Efficient High-Speed CORDIC Algorithm Using Parallel-Prefix Adders (PPA). In: Dutta, D., Kar, H., Kumar, C., Bhadauria, V. (eds) Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol 587. Springer, Singapore. https://doi.org/10.1007/978-981-32-9775-3_73
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DOI: https://doi.org/10.1007/978-981-32-9775-3_73
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