Abstract
Design of high-scalable quantum information processor (QIP) towards achieving quantum supremacy is still now in infancy due to catastrophic obstacles from decoherence. In way to address this problem, the use of quantum error correction code (QECC) and fault-tolerant circuit is highly enticieable, which further promises not only to protect extreme fragile quantum state from decoherence but also from other noises. It is seen that the fault-tolerant property can be achieved by the use of transversal primitive unitary operators. Here, we show the design of fault-tolerant implementation of BCD-to-Excess-3 and 2’s complement code converter which is pivotal in the design of high-scalable QIP. In this transformation process, first we transform the input circuit to an intermediate form where we obtain its NCV-based representation. In the second phase, this design is extensively used to form the fault-tolerant design. We also have compared our design with some of the existing works and have registered 39% improvement in design cost. In terms of T-count and T-depth metrics, our proposed designs also provide near-optimal solution.
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References
Shor, P.W.: Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer. SIAM J. Sci. Statist. Comput. 26, 1484–1509 (1997)
Grover, L.K.: Quantum mechanics helps in searching for a needle in a haystack. Phys. Rev. Lett. 79, 325–328 (1997)
Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Develop. 5(3), 183–191 (1961)
Moore, G.E.: Cramming more components onto integrated circuits. Electronics 38(8) (1965)
Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Develop. 17(6), 525–532 (1973).https://doi.org/10.1147/rd.176.0525
Feynman, R.P.: Quantum mechanical computers. Found. Phys. 16, 507–531 (1986)
https://blog.usejournal.com/quantum-computings-promise-for-the-brave&-new-world-fa15b651cced
Wootters, W.K., Zurek, W.H.: A single quantum cannot be cloned. Nature 299, 802–803 (1982)
DiVincenzo, D.P.: The physical implementation of quantum computation. Fortschr. Phys. 48, 771
Preskill, J.: Fault tolerant quantum computation. In: Lo, H.K., Popescu, S., Spiller, T. (eds.), Introduction to Quantum Computation and Information, Chap. 8, p. 213. World Scientific, River Edge, NJ (1998). https://arxiv.org/abs/quant-ph/9712048
Fowler, A.G., Mariantoni, M., Martinis, J.M., Cleland, A.N.: Surface codes: towards practical large-scale quantum computation. Phys. Rev. A 86, 032324 (2012)
Fowler, A.G., Stephens, A.M., Groszkowski, P.: High threshold universal quantum computation on the surface code. Phys. Rev. A. 80, 052312 (2009)
Paetznick, A., Reichard, B.W.: Universal fault-tolerant quantum computation with only transver-sal gates and error correction. Phys. Rev. Lett. 111(9), 090505 (2013)
Jones, N.C., Whitfield, J.D., McMahon, P.L., Yung, M.H., Meter, R.V., Aspuru-Guzik, A., Yamamoto, Y.: Faster quantum chemistry simulation on fault-tolerant quantum computers. New. J. Phys. 14, 115023 (2012)
Saravanan, M., Manic, K.S.: Energy efficient code converters using reversible logic gates. In: IEEE International Conference Green High Performance Computing (ICGHPC), pp. 1–6 (2013)
Thapliyal, H., Arabnia, H.R., Bajpai, R., Sharma, K.K.: Design of testable reversible sequential circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(7), 1201–1209 (2013)
Haghparast, M., Hajizadeh, M., Hajizadeh, R., Bashiri, R.: On the synthesis of different nanometric reversible converters. Middle-East J. Sci. Res. 7, 715–720 (2011)
Maity, H., Barik, A.K., Biswas, A., Bhattacharjee, A.K., Pal, A.: J. Circuit. Syst. Comput. 27, 1850184 (2018)
Maity, H., Biswas, A., Pal, A., Bhattacharjee, A.K.: Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate. Int. J. Quant. Inf. 16(07), 1850061 (2018)
Biswal, L., Das, R., Bandyopadhyay, C., Chattopadhyay, A., Rahaman, H.: A template-based technique for efficient Clifford+T-based quantum circuit implementation. Microelectron. J. 81, 58–68 (2018)
Shukla, V., Singh, O.P., Mishra, G.R., Tiwari, R.K.: Design of a 4-bit 2’s complement reversible circuit for arithmetic logic unit applications. In: Proceedings of International Conference in Communication Computing and Information Technology (ICCCMIT) Special Issue of International Journal of Computer Applications, pp. 1–5. Chennai, India (2012)
Gandhi, M., Devishree, J., Venkatesh, J., Sathish Mohan, S.: Design of reversible circuits for code converter and binary incrementer. J. Inf. Technol. Mech. Eng. (IJITME) 1, 24–33 (2014)
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Biswal, L., Bandyopadhyay, C., Rahaman, H. (2020). Clifford+T-based Fault-Tolerant Quantum Implementation of Code Converter Circuit. In: Pant, M., Kumar Sharma, T., Arya, R., Sahana, B., Zolfagharinia, H. (eds) Soft Computing: Theories and Applications. Advances in Intelligent Systems and Computing, vol 1154. Springer, Singapore. https://doi.org/10.1007/978-981-15-4032-5_58
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DOI: https://doi.org/10.1007/978-981-15-4032-5_58
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