Abstract
Coherent and power-efficient processor-memory interconnects are of great importance for kilo-core processor design. This paper proposes a hybrid photonic architecture for such interconnection. Specifically, a bandwidth-efficient photonic network which also supports coherence management is used for memory accesses between last-level HBM caches and off-chip HMC memory pools. Simulation results show that the hybrid network achieves up to 11% of system speedup and up to 6 times of energy savings, when compared to conventional electric interconnects.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Schulte, M.J., Ignatowski, M., Loh, G.H., et al.: Achieving exascale capabilities through heterogeneous computing. IEEE Micro 35(4), 26–36 (2015)
Borkar, S.: Thousand core chips a technology perspective. In: Proceedings of 44th ACM/IEEE Design Automation Conference, pp. 746–749 (2007)
Sanchez, D., et al.: An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans. Archit. Code Optim. 7(1), 4 (2010)
Dong, P., et al.: Silicon photonic devices and integrated circuits. Nanophotonics 3, 215–228 (2014)
Iyer, S.S.: Three-dimensional integration: an industry perspective. MRS Bull. 40(03), 225–232 (2015)
JEDEC Homepage. https://www.jedec.org/. Accessed 21 June 2017
HMC Homepage. http://www.hybridmemorycude.org/. Accessed 21 June 2017
Shacham, A., Bergman, K., Carloni, L.P.: Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans. Comput. 57(9), 1246–1260 (2008)
Vantrease, D., et al.: Corona: system implications of emerging nanophotonic technology. In: Proceedings of 35th International Symposium on Computer Architecture, pp. 153–164 (2008)
Chan, J., et al.: PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks. In: Proceedings on Design, Automation & Test in Europe (2010)
Kahng, A.B., et al.: ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: Proceedings on Design, Automation & Test in Europe (2009)
Sorin, D.J., et al.: A Primer on Memory Consistency and Cache Coherence. Synthesis Lectures on Computer Architecture #16. Morgan & Claypool Publishers, San Rafael (2011)
Feng, C., Lu, Z., Jantsch, A., Zhang, M., Xing, Z.: Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(6), 1053–1066 (2013)
Feng, C., Lu, Z., Jantsch, A., Zhang, M., Yang, X.: Support efficient and fault-tolerant multicast in bufferless network-on-chip. IEICE Trans. Inf. Syst. E95-D(4), 1052–1061 (2012)
Feng, Q., Peng, C., Ren, S., Zhou, H., Deng, R.: A high throughput power-efficient optical memory subsystem for kilo-core processor. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds.) NCCET 2017. CCIS, vol. 600, pp. 52–62. Springer, Singapore (2018). https://doi.org/10.1007/978-981-10-7844-6_6
Ahmed, A.B., Meyer, M.C., Okuyama, Y., et al.: Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC). In: International Conference on Information Science and Control Engineering, pp. 202–206 (2015)
Kodi, A.K., et al.: Scalable power-efficient kilo-core photonic-wireless NoC architectures. In: International Parallel and Distributed Processing Symposium, pp. 1010–1019 (2018)
Meyer, M.C., Okuyama, Y., Abdallah, A.B., et al.: A power estimation method for mesh-based photonic NoC routing algorithms. In: International Symposium on Computing and Networking, pp. 451–453 (2016)
Woo, S.C., et al.: The SPLASH-2 programs: characterization and methodological considerations. In: International Symposium on Computer Architecture, vol. 23, no. 2, pp. 24–36 (1995)
Miller, J.E., et al.: Graphite: a distributed parallel simulator for multicores. In: 16th IEEE Symposium on High-Performance Computer Architecture, January 2010
Acknowledgement
This work is supported by the National Natural Science Foundation of China under Grant 61402502, Grant 61402497 and Grant 61472432, and in part by HGJ under Grant 2018ZX01029-103.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Feng, Q., Wang, J., Zhou, H., Dou, W. (2019). A Coherent and Power-Efficient Optical Memory Access Network for Kilo-Core Processor. In: Xu, W., Xiao, L., Li, J., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2019. Communications in Computer and Information Science, vol 1146. Springer, Singapore. https://doi.org/10.1007/978-981-15-1850-8_5
Download citation
DOI: https://doi.org/10.1007/978-981-15-1850-8_5
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-1849-2
Online ISBN: 978-981-15-1850-8
eBook Packages: Computer ScienceComputer Science (R0)
