Abstract
The paper focuses on basics of analog-to-digital conversion. Various types of analog-to-digital converters are available. Here, the basics of one of its type, sigma delta, is discussed, starting from quantization and then moving to first-, second-, and third-order structures. The SNR obtained is 62 dB and 61.4 B, 91.9, respectively. Moving toward higher order with same approach causes instability. Therefore, an architecture using feedback or feedforward may be used. Some of the popular higher-order topologies are based on feedback and feedforward arrangements: cascade of resonator-feedback form (CRFB), cascade of resonator-feedforward form (CRFF), cascade of integrator-feedback form (CIFB), and cascade of resonator-feedforward form (CIFF) with SNR achieved as 140 dB, 153.6 dB, 141.8 dB, and 164.4 dB, respectively.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Schreier, R., Temes, G.C.: Understanding Delta Sigma Converters. IEEE press
Cherry, J., Snelgrove, W.: Continuos Time Delta Sigma Modulators for High Speed A/D Conversion. Kluwer Academic Publishers
Park, M., Perrott, M.: A 78 dB SNDR 87 mW, 20 MHz bandwidth continuous–time ∑Δ ADC with VCO-based integrator and quantizer implemented in 0.13 µm at CMOS. IEEE J. Solid State Circuits 44(12), 33 (2009)
Dendouga, A., Bouguachal, N., Kouda, S., Barra, S., Lakehal, B.: Contribution to modeling of a non ideal ∑Δ modulator. J. Comput. Electron. (2012)
Silva, J., Moon, U., Steensgaard, J., Temes, G.C.: Wideband low-distortion delta sigma ADC topology. Electron. Lett. 37(12), 737–738 (2001)
Temes, G.: Finite amplifier gain and bandwidth effects in switched capacitor filters. IEEE J. Solid States 15, 358–361 (1980)
Harrison, R.R., Charles, C.: A low power low noise CMOS amplifier for neural recording applications. IEEE J. Solid State Circuit 38(6) (2003)
Matsukawa, K., Nitani, Y., Takayama, M., Obata, K., Dosho, S., Matsukawa, A.: A fifth order continuos time ∑Δ modulator with single op-amp resonator. IEEE J. Solid State Circuit 45(4) (2010)
Mitteregger, G., Ebner, C., Mechnig, S., Blon, T., Holuigue, C., Romani, E.: A 20-mW, 640-MHz, CMOS continuous-time ADC with 20 MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB. IEEE J. Solid State Circuits 41(12), 2641–2649 (2006)
Steensgaard, J.: High performances data converters. Ph.D. thesis, Technical University of Denmar, Department of Information Technology (1999)
Donida, A., Cellius, R., Nagari, A., Baschirotto, A.: A 40 nm CMOS 1.1 V, 101 dB dynamic range, 1.7 mW continuous time. IEEE Regul. Pap. 62(3) (2015)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Malhotra, D., Aggarwal, A. (2020). Design and Analysis of Higher-Order Sigma Delta Modulator. In: Pati, B., Panigrahi, C., Buyya, R., Li, KC. (eds) Advanced Computing and Intelligent Engineering. Advances in Intelligent Systems and Computing, vol 1089. Springer, Singapore. https://doi.org/10.1007/978-981-15-1483-8_5
Download citation
DOI: https://doi.org/10.1007/978-981-15-1483-8_5
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-1482-1
Online ISBN: 978-981-15-1483-8
eBook Packages: EngineeringEngineering (R0)