Novel Application of FeFETs to NAND Flash Memory Circuits

Abstract

A 64 kbit (kb) one-transistor-type ferroelectric memory array and peripheral logic circuits were integrated and characterized. N-channel Pt/SrBi₂Ta₂O₉/Hf–Al–O/Si ferroelectric-gate field-effect transistors (FeFETs) were used as the memory cells. The array was designed as a NAND flash memory, which had 32 blocks and 8 word lines × 256 bit lines per block. The bit-line and block selector logic circuits were represented by logic NOT and NAND units that were constructed by the complimentary structure of an n-channel FeFET and a p-channel FeFET. The erase, program, and nondestructive read operations were demonstrated for all blocks. The reading of the memory cells showed a clear separation of their erased and all “1”-programmed states. Threshold-voltage retention of one block showed no significant degradation after 2 days. To program arbitrary “1” and “0” patterns a single-cell self-boost program scheme was introduced that can reduce program-disturb and power dissipation, and in fact very low program-inhibit-bit-line voltage (≤1.0 V) was achieved. Using this scheme the memory cells were programmed in “1” and “0” checkered pattern, and two distinguishable threshold-voltage distributions of 1 block (2 k cells) could be read out.