Abstract
S-Box is implemented normally by using lookup tables (LUT) in which 256 predefined values of S-Box and the same numbers for Inverse S-Box are stored in a ROM, it offers a shorter critical depth, it is suitable for FPGA implementation in terms of gate count. In high speed pipelined designs unbreakable delay of LUT becomes a drawback. The efficiency of AES hardware implementation in terms of speed, security, size, and power consumption largely depends on its architecture Every attempt has been made by researchers to optimize one or more parameters for some specific application, either to reduce the chip area, power consumption or to increase efficiency, throughput, and security level. The different applications of society requirements demand different parameters with respect to size for mobile applications, high-speed processing for a quick response. S-Box transformation in AES Implementation is the nonlinear transformation and it provides confusion part in encryption of data processing and contributes a significant part in achieving high security. CFA-based optimization is used for reducing the area for FPGA or VLSI designs for compact mobile applications, the data security is ensured by adopting different masking techniques.
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Akkar, M.-L., Giraud, C.: An implementation of DES and AES, secure against some attacks. In: International Workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin (2001)
Blömer, J., Guajardo, J., Krummel, V.: Provably secure masking of AES. In: International Workshop on Selected Areas in Cryptography. Springer, Berlin (2004)
Canright, D.: A very compact Rijndael S-box (2004)
Canright, D., Batina, L.: A very compact “perfectly masked” S-box for AES. In: International Conference on Applied Cryptography and Network Security. Springer, Berlin (2008)
Chari, S., et al.: Towards sound approaches to counteract power-analysis attacks. In: Annual International Cryptology Conference. Springer, Berlin (1999)
Fan, C.-P., Hwang, J.-K.: Implementations of high throughput sequential and fully pipelined AES processors on FPGA. In: International Symposium on Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007. IEEE (2007)
Fan, C.-P., Hwang, J.-K.: Implementations of high throughput sequential and fully pipelined AES processors on FPGA. In: International Symposium on Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007. IEEE (2007)
Ishai, Y., Sahai, A., Wagner, D.: Private circuits: securing hardware against probing attacks. In: Annual International Cryptology Conference. Springer, Berlin (2003)
Joye, M., Paillier, P., Schoenmakers, B.: On second-order differential power analysis. In: International Workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin (2005)
Kaur, A., Bhardwaj, P., Kumar, N.: FPGA implementation of efficient hardware for the advanced encryption standard. Int. J. Innov. Technol. Explor. Eng. 2(3), 186–189 (2013)
Kömmerling, O., Kuhn, M.G.: Design principles for tamper-resistant smartcard processors. Smartcard 99, 9–20 (1999)
Mangard, S., Pramstaller, N., Oswald, E.: Successfully attacking masked AES hardware implementations. In: International Workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin (2005)
Mangard, S., Schramm, K.: Pinpointing the side-channel leakage of masked AES hardware implementations. In: International Workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin (2006)
Oswald, E., et al.: A side-channel analysis resistant description of the AES S-box. In: International Workshop on Fast Software Encryption. Springer, Berlin (2005)
Regazzoni, F., Wang, Y., Standaert, F.-X.: FPGA implementations of the AES masked against power analysis attacks. Proc COSADE 2011, 56–66 (2011)
Rouvroy, G., et al.: Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. vol. 2. IEEE (2004)
Satoh, A., et al.: A compact Rijndael hardware architecture with S-box optimization. In: International Conference on the Theory and Application of Cryptology and Information Security. Springer, Berlin (2001)
Kim, H., Hong, S., Lim, J.: A fast and provably secure higher-order masking of AES S-box. In: International Workshop on Cryptographic Hardware and Embedded Systems. Springer, Berlin (2011)
Stevens, K., Mohamed, O.A.: Single-chip FPGA implementation of a pipelined, memory-based AES Rijndael encryption design. In: Canadian Conference on Electrical and Computer Engineering, 2005. IEEE (2005)
Hoang, T.: An efficient FPGA implementation of the advanced encryption standard algorithm. In: 2012 IEEE RIVF International Conference on Computing and Communication Technologies, Research, Innovation, and Vision for the Future (RIVF). IEEE (2012)
Thulasimani, L., Madheswaran, M.: A single chip design and implementation of aes-128/192/256 encryption algorithms. Int. J. Eng. Sci. Technol. 2(5), 1052–1059 (2010)
Wolkerstorfer, J., Oswald, E., Lamberger, M.: An ASIC implementation of the AES S boxes. In: Cryptographers’ Track at the RSA Conference. Springer, Berlin (2002)
Singh, A., Talwar, Y., Prasad, A.: Highly secure and fast AES algorithm implementation on FPGA with 256 bit key size. Int. J. Innov. Technol. Explor. Eng. (IJITEE) ISSN: 2278-3075 (on line) in 6(7), 8 (2016)
Singh, A., Prasad, A., Talwar, Y.: SCADA security issues and FPGA implementation of AES—A review. In: 2016 2nd International Conference on Next Generation Computing Technologies (NGCT). IEEE (2016)
Talwar Y., VeniMadhawan, C.E. Navin, R.: On partial linearization of byte substitution transformation of Rijindael—The AES. J. Comput. Sci. 2(2), 48–52. Science Publications; New York, USA (2006)
Wong, M.M., et al.: Construction of optimum composite field architecture for compact high-throughput aes s-boxes. In: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(6), 1151–1155 (2012)
Zhang, X., Parhi, K.K.: High-speed VLSI architectures for the AES algorithm. In: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(9), 957–967 (2004)
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Singh, A., Prasad, A., Talwar, Y. (2020). Compact and Secure S-Box Implementations of AES—A Review. In: Somani, A.K., Shekhawat, R.S., Mundra, A., Srivastava, S., Verma, V.K. (eds) Smart Systems and IoT: Innovations in Computing. Smart Innovation, Systems and Technologies, vol 141. Springer, Singapore. https://doi.org/10.1007/978-981-13-8406-6_80
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