Abstract
The speed of high-speed railway in China is constantly increasing, and the demand for safety and reliability becomes more and more apparent. Therefore, it is especially important to collect and transmit high-speed data accurately, so high-speed data acquisition system emerged. Aiming at the problem of transmission packet loss in high-speed data acquisition system, a retransmission protocol is proposed for Automatic Repeat Request (ARQ) communication, which is implemented on field-programmable gate array (FPGA). This design compares several common retransmission protocols to select the optimal scheme. And the feasibility of the high-speed rail transponder system is analyzed. On the basis of that, this design takes full advantage of the flexibility and reconfigurability of the FPGA, uses the hardware description language VerilogHDL, uses Quartus II 13.1 for synthesis and routing, and finally verifies on the Cyclone VE series 5CEFA4F23F. The design has the advantages of convenient application and upgrade, good portability and versatility while solving the problem of packet loss.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Kai, L: Ethernet-based data acquisition system implemented on FPGA. Wuhan University of Science and Technology (2009)
Ning, Y., Guo, Z., Shen, S., Peng, B.: Design of data acquisition and storage system based on the FPGA. Procedia Eng. (2012)
Zhong, G.: Design of high speed data acquisition system based on FPGA. Nanjing University (2013)
Wu, C., Xu, J., Jiang, J.: Research and implementation of gigabit ether-net interface based on FPGA. Mod. Electron. Tech. 41(09), 1–5 (2018)
Shi, P.: Design of FPGA bidirectional data transmission system based on Gigabit Ethernet. Xidian University (2014)
Yang, J.: Research on ARQ Mechanism in MAC Layer of 802.16 m System. University of Electronic Science and Technology of China (2012)
Yi, Q.: Design and FPGA Implementation of Ten Gigabit Ethernet MAC Controller. IEEE Beijing Section, Global Union Academy of Science and Technology, Chongqing Global Union Academy of Science and Technology, Chongqing Geeks Education Technology Co., Ltd. Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC 2017). IEEE Beijing Section, Global Union Academy of Science and Technology, Chongqing Global Union Academy of Science and Technology, Chongqing Geeks Education Technology Co., Ltd:IEEE BEIJING SECTION (2017)
Xia, Y.: 10 Gigabit ethernet TCP frame data registration algorithm based on FPGA. In: Proceedings of 2016 2nd International Conference on Mechanical, Electronic and Information Technology Engineering (ICMITE 2016) (2016)
Zhong, Z.: Top-down FPGA design. Electronic Products World (1998)
Zou, L., Tian, L.: Design and implementation of gigabit network data acquisition system based on FPGA. Digital Technol. Appl. 136 (2011)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Li, X., Lv, J. (2019). Design and Implementation of ARQ Mechanism in High-Speed Data Acquisition System. In: Sun, S., Fu, M., Xu, L. (eds) Signal and Information Processing, Networking and Computers. ICSINC 2018. Lecture Notes in Electrical Engineering, vol 550. Springer, Singapore. https://doi.org/10.1007/978-981-13-7123-3_7
Download citation
DOI: https://doi.org/10.1007/978-981-13-7123-3_7
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-7122-6
Online ISBN: 978-981-13-7123-3
eBook Packages: EngineeringEngineering (R0)