Low Leakage Read Write Enhanced 9T SRAM Cell

Abstract

In deep submicrometer technology (below 65 nm), SRAM designs suffer from high leakage and low stability issues. This paper presents a low leakage highly stable SRAM cell with read-write enhanced circuitry. The proposed SRAM performs read-write operation through single bitline and have separate read-write circuitry. It consists of a sleep transistor (shared by an array) in the read path, that remains OFF during hold and write mode to suppress the bitline leakage. It shows enhanced write ability and low leakage due to stacking effect in left inverter. Additionally, one data dependent charge pump circuit is used to prevent read bitline leakage while reading logic ‘1’ thereby improving the sense margin of bitline. Various design parameters such as read static noise margin (RSNM), read access time ($T_{RA}$), write access time ($T_{WA}$), leakage power and write ability of differential 6T (D6T), single bitline 9T (SB9T) and proposed (RWE9T) SRAM cell have been discussed. HSPICE simulations are performed using 32 nm PTM (LP). The proposed SRAM shows 2.14x improvement in RSNM as compared to D6T. Also, it shows an improvement of 2x and 1.38x in write ‘1’ margin as compared to D6T and SB9T and 1.38x in write ‘0’ margin than SB9T SRAM cell. An improvement of 1.75x in $T_{RA}$ and 3.62x in write ‘0’ access time as compared to SB9T is shown at a penalty of write ‘1’ access time. RWE9T consumes 4.5x and 4.12x less leakage power as compared to D6T and SB9T at VDD = 0.9 V.