Abstract
Use of bus architecture based communication with increasing processing elements in System-on-Chip (SoC) leads to severe degradation of performance and speed of the system. This bottleneck is overcome with the introduction of Network-on-Chips (NoCs). NoCs assist in communication between cores on a single chip using router based packet switching technique. Due to miniaturization, NoCs like every Integrated circuit is prone to different kinds of faults which can be transient, intermittent or permanent. A fault in any one component of such a crucial network can degrade performance leaving other components non-usable. This paper presents a novel Fault-Tolerant routing Algorithm for Mesh-of-Tree (MoT) topology in presence of stem faults. The proposed technique is compared with routing technique already in the literature. The results show improvements in terms of number of packets reaching destination routers from any source routers in MoT network in presence of faults, by scaling the topology size.
This work is partially supported by the research project No. ECR/2016/001389 Dt. 06/03/2017, sponsored by the SERB, Government of India.
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Shah, M., Upadhyay, M., Bhanu, P.V., Soumya, J., Cenkeramaddi, L.R. (2019). A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_38
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DOI: https://doi.org/10.1007/978-981-13-5950-7_38
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