Abstract
Simulation based investigation of Recessed Dual-Gate MISHEMT on sapphire substrate has been presented in this work using ATLAS simulation software. Various DC performance parameters such as: threshold voltage shift, drain current and transconductance has been compared for different gate combinations. Threshold voltage variation is observed to be nearly same if gate1 is recessed only or both gates are recessed. Positive shift in threshold voltage has been observed as the depth of gate recess is increased from 0 nm to 8 nm. Enhancement in negative junction depth from 10 nm to 18 nm results in the shift in threshold voltage towards positive i.e. −3.5 V to −2.45 V. This improvement in threshold voltage is due to the reduction in barrier thickness with increase in negative junction depth. DC performance has also been evaluated for the device with high-k gate dielectric such as HfO2 and TiO2 for non-recessed and recessed device. The parameters like gate oxide and work function variation results in the shift of threshold voltage from −3.5 V to 0 V in recessed Dual-Gate MISHEMT.
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Acknowledgement
One of the authors, Preeti Singh, would like to thank Ministry of Science and Technology, Department of Science and Technology (SR/WOS-A/ET-143/2017), Government of India and University of Delhi for providing necessary financial assistance during the course of this research work.
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Singh, P., Kumari, V., Saxena, M., Gupta, M. (2019). Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation Study. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_33
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DOI: https://doi.org/10.1007/978-981-13-5950-7_33
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