High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR Platform

Abstract

This paper proposes a High Level Synthesis (HLS) design methodology that translates complex algorithms modeled in high level language to hardware description. The existing HLS strategies fails to provide adequate abstraction to the underlying hardware details and thus limits software programmers from designing complex and advanced cipher algorithms. In this paper the method of generating synthesizable Register Transfer Level (RTL) design from algorithm is accomplished through an open framework called AHIR, an acronym for a hardware intermediate representation. The integrated design flow intends to generate layout from algorithm with minimal human intervention and thus offers software programmers with ample opportunities to design application specific digital hardware. The paper discusses several highlights of the design flow including savings in verification, rapid prototyping and shorter time to market together with various performance overheads. The cipher algorithms implemented in this paper includes the widely accepted Advanced Encryption Standard (AES) along with other established lightweight algorithms namely PRESENT, Light Encryption Device (LED) which are effective for resource constrained applications. A comparative performance analysis was carried out between the high level design approach and the traditional RTL style based on their FPGA and ASIC implementation.