Abstract
This paper presents a high matching charge pump with low noise. Two pairs of charge pumps in differential structure alleviate charge sharing and improve static mismatch. This simple structure with minimum number of transistors can reduce the noise of CP. A differential low amplitude buffer stage is proposed to reduce the dynamic mismatch of CP. A 3.125 GHz PLL is implemented with the proposed charge pumps in 65 nm CMOS process. In simulation, the proposed CP achieved good static mismatch and dynamic mismatch in a dynamic range larger than half VDD. The noise simulated at 1 kHz achieved −227 dB. The reference spur measured at 25 MHz was lower than −51.5 dBc. The test results show the good performance of proposed CPPLL.
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Acknowledgments
This research was supported by National Natural Science Foundation of China Program (No. 61772540).
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Yuan, H., Guo, Y. (2019). A High-Matching Low Noise Differential Charge Pump for PLL. In: Xu, W., Xiao, L., Li, J., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2018. Communications in Computer and Information Science, vol 994. Springer, Singapore. https://doi.org/10.1007/978-981-13-5919-4_9
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DOI: https://doi.org/10.1007/978-981-13-5919-4_9
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