Abstract
In this paper, we present speculation-driven prefix topology-based finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The core objective of our proposed framework is to maximize the prefix accumulation in the application of RNS to the design high-performance FIR filter design. To achieve this, we propose a RAM-based reverse conversion model followed by accumulation to produce the modular multiplication. The proposed RNS design makes use of block RAMs available in FPGA devices and appropriate moduli sets in order to accommodate FIR convolution results. The proposed approach is formulated to design precomputed reverse converters for different moduli sets and to implement FPGA as target devices. As a result, we propose speculative parallel prefix topology-based post accumulation technique for RNS-based multiplication, along with a high-performance FIR filter architecture that employs independent modulo channel RNS arithmetic. Experiment results of RNS-FIR design over different number of FIR taps and input operand word lengths alongside with appropriate moduli sets that suits to accommodate FIR end results.
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Reddy Hemantha, G., Varadarajan, S., Giri Prasad, M.N. (2019). FPGA Implementation of Speculative Prefix Accumulation-Driven RNS for High-Performance FIR Filter. In: Saini, H., Singh, R., Kumar, G., Rather, G., Santhi, K. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, vol 65. Springer, Singapore. https://doi.org/10.1007/978-981-13-3765-9_38
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DOI: https://doi.org/10.1007/978-981-13-3765-9_38
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