Abstract
The proposed work aims at generating a diagnostic test set which is a compact test set derived from a large set of test vectors generated from any automatic test pattern generator (ATPG). This diagnostic test set is required to find out the exact location of the faults. The patterns generated from the ATPG may be sufficient to find out whether the circuit is fault free or not, but will not give the location of the fault. Hence, the proposed method aims at identifying the exact location of the faults. The experiment has been carried out on several ISCAS’85 and ISCAS’89 benchmark circuits.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Anita, J.P., Sudheesh, P.: Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams. Int. J. High Perform. Syst. Arch. 6(1), 51–60 (2016)
Ye, J., Zhang, X., Hu, Y., Li, X.: Substantial fault pair at-a-time (SFPAT): an automatic diagnostic pattern generation method. In: Proceedings of ATS, pp. 192–197, Dec 2010
McCluskey, E.G., Clegg, F.W.: Fault equivalence in combinational logic networks. IEEE Trans. Comput. C-20(11), 1286–1293 (1971)
Mohan, N., Anita, J.P.: A zero suppressed binary decision diagram based test set relaxation for single and multiple stuck-at faults. Int. J. Math. Model. Numer. Optim. 7(1), 83–96 (2016)
Lin, Y.-C., Lu, F., Cheng, K.T.: Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), 932–942 (2007)
Tang, H., Reddy, S.M.: Diagnosis of multiple faults based on fault-tuple equivalence tree. In: Proceedings of DFTS, pp. 217–225, Oct 2011
Pomeranz, I.: A test selection procedure for improving the accuracy of defect diagnosis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(8), 2759–2767 (2016)
Tang, H., Manish, S., Rajski, J., Keim, M., Benware, B.: Analyzing volume diagnosis results with statistical learning for yield improvement. In: Proceedings of ETS, pp. 145–150, May 2007
Pomeranz, I.: Improving the accuracy of defect diagnosis by considering reduced diagnostic information. In: Proceedings of VTS, p. 16, Apr 2015
Kundu, S., Jha, A., Chattopadhyay, S., Sengupta, I., Kapur, R.: Framework for multiple-fault diagnosis based on multiple fault simulation using particle swarm optimization. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(3), 696–700 (2014)
Veneris, A., Chang, R., Abadir, M., Amiri, M.: Fault equivalence and diagnostic test generation using ATPG. In: Proceedings of ISCAS, pp. V-221–V-224, May 2004
Lee, H., Ha, D.: ATALANTA: an efficient ATPG for combinational circuits. Technical Report 93-12, Virginia Polytech. Inst. State Univ., Blacksburg, VA, USA, pp. 12–93
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Madhan, B., Anita, J.P. (2019). Improving Diagnostic Test Coverage from Detection Test Set for Logic Circuits. In: Wang, J., Reddy, G., Prasad, V., Reddy, V. (eds) Soft Computing and Signal Processing . Advances in Intelligent Systems and Computing, vol 898. Springer, Singapore. https://doi.org/10.1007/978-981-13-3393-4_46
Download citation
DOI: https://doi.org/10.1007/978-981-13-3393-4_46
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-3392-7
Online ISBN: 978-981-13-3393-4
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)