Abstract
In this paper, an architecture is presented for a fused floating-point three operand adder unit. This adder executes two additions within a single unit. The purpose of this execution is to lessen total delay, die area, and power consumption in contrast with traditional addition method. Various optimization techniques including exponent comparison, alignment of significands, leading zero detection, addition, and rounding are used to diminish total delay, die area, and power consumption. In addition to this, the comparison is described of different blocks in term for die area, total delay, and power consumption. The proposed scheme is designed and implemented on Xilinx ISE Design 14.7 and synthesized on Synopsis.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Zuras, D., Cowlishaw, M., Aiken, A., Applegate, M., Bailey, D., Bass, S., et al. (2008). IEEE standard for floating-point arithmetic. IEEE Standards, 754–2008, 1–70.
Sohn, J., & Swartzlander, E. E. (2014). A fused floating-point three-term adder. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(10), 2842–2850.
Popalghat, M., & Palsodkar, P. (2016). Implementation of fused floating point three term adder unit. In 2016 International Conference on Communication and Signal Processing (ICCSP) (pp. 1343–1346). IEEE.
Drusya, P., & Jacob, V. (2016). Area efficient fused floating point three term adder. In International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) (pp. 1621–1625). IEEE.
Sohn, J., & Swartzlander, E. E. (2012). Improved architectures for a fused floating-point add-subtract unit. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(10), 2285–2291.
Tenca, A.F. (2009). Multi-operand floating-point addition. In 2009 19th IEEE Symposium on Computer Arithmetic, ARITH 2009. (pp. 161–168). IEEE
Seidel, P. M., & Even, G. (2004). Delay-optimized implementation of IEEE floating-point addition. IEEE Transactions on Computers, 53(2), 97–113.
Tao, Y., Deyuan, G., Xiaoya, F., & Xianglong, R. (2012). Three-operand floating-point adder. In 2012 IEEE 12th International Conference on Computer and Information Technology (CIT) (pp. 192–196). IEEE.
Underwood, K. (2004). Fpgas vs. cpus: trends in peak floating-point performance. In Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays (pp. 171–180). ACM.
Monniaux, D. (2008). The pitfalls of verifying floating-point computations. ACM Transactions on Programming Languages and Systems (TOPLAS), 30(3), 12.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Kumar, A., Kumar, S., Raj Gautam, P., Verma, A., Rashid, T. (2019). Performance Evaluation of Multi-operands Floating-Point Adder. In: Khare, A., Tiwary, U., Sethi, I., Singh, N. (eds) Recent Trends in Communication, Computing, and Electronics. Lecture Notes in Electrical Engineering, vol 524. Springer, Singapore. https://doi.org/10.1007/978-981-13-2685-1_51
Download citation
DOI: https://doi.org/10.1007/978-981-13-2685-1_51
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-2684-4
Online ISBN: 978-981-13-2685-1
eBook Packages: EngineeringEngineering (R0)