Abstract
This paper proposes a cylindrical vertical Gate-All-Around Transistor with nanowire of compound III-V semiconductor material In0.53Ga0.47As n-type device with channel length of 10 nm. The effect of variation of channel diameter and spacer length on the performance of the device is simulated. The device gives an acceptable Subthreshold Slope and Drain Induced Barrier Lowering along with satisfactory ION/IOFF ratio. The device is simulated in Sentaurus Synopsys using Hydrodynamic model for III-V semiconductors with Poisson equation to give the transfer characteristics.
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Acknowledgements
The authors would like to thank Indian Nanoelectronics Users Program (INUP), IIT-B for accepting our project and helping us in the same.
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Kulkarni, S., Joshi, S., Bade, D., Subramaniam, S. (2019). Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire). In: Iyer, B., Nalbalwar, S., Pathak, N. (eds) Computing, Communication and Signal Processing . Advances in Intelligent Systems and Computing, vol 810. Springer, Singapore. https://doi.org/10.1007/978-981-13-1513-8_62
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DOI: https://doi.org/10.1007/978-981-13-1513-8_62
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