Abstract
This paper describes a high-speed data readout method for a large-scale front-end electronics in the JESD204B protocol-like transmission protocol implemented in a FPGA, in addition to a reading out for a commercial ADC. A prototype board including analog signal processing, digitization, digital processing and control in FPGA, and data transmission has been designed and together with a lab designed data receiver board, a demo system has been setup for this study of new method. The JESD204B protocol is implemented in FPGA, which is compared and verified by the commercial ADC output and the test results are showed satisfactory.
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References
JEDEC Standard: Serial Interface for Data Converters JESD204B.01
Lin, H.-C.: Research on self-trigger front-end unit for low frequency radio detection. Ph.D., thesis
Acknowledgments
This project has been Supported by National Natural Science Foundation of China (Grant No. 11435013) and Ministry of Science and Technology of the People’s Republic of China (Grant No. 2016YFA0400104).
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Liu, Z. et al. (2018). Study of Front-End High Speed Readout Based on JESD204B. In: Liu, ZA. (eds) Proceedings of International Conference on Technology and Instrumentation in Particle Physics 2017. TIPP 2017. Springer Proceedings in Physics, vol 212. Springer, Singapore. https://doi.org/10.1007/978-981-13-1313-4_45
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DOI: https://doi.org/10.1007/978-981-13-1313-4_45
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Online ISBN: 978-981-13-1313-4
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