Abstract
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
This chapter is a partial reprint of R. Micheloni, S. Aritome, L. Crippa, “Array architectures for 3D NAND Flash Memories” in Proceedings of the IEEE, vol. 105, no. 9, pp. 1634–1649, Sept. 2017. © 2017 IEEE.
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Micheloni, R., Aritome, S., Crippa, L. (2018). 3D NAND Flash Memories. In: Micheloni, R., Marelli, A., Eshghi, K. (eds) Inside Solid State Drives (SSDs). Springer Series in Advanced Microelectronics, vol 37. Springer, Singapore. https://doi.org/10.1007/978-981-13-0599-3_5
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