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Low-Density Parity-Check (LDPC) Codes

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Inside Solid State Drives (SSDs)

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 37))

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Abstract

In this chapter, low-density parity-check (LDPC) codes , a class of powerful iteratively decodable error correcting codes, are introduced. The chapter first reviews some basic concepts and results in information theory such as Shannon’s channel capacity and channel coding theorem . It then overviews the flash memory channel model. Next, it addresses binary LDPC codes describing both their structure and efficient implementation, and their belief propagation and reduced-complexity decoding algorithms. Non-binary LDPC codes and their belief propagation decoding algorithm are also addressed. Finally simulation results are provided.

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Notes

  1. 1.

    The capacity of the BSC only depends on the crossover probability and not on the values assumed by X and Y.

  2. 2.

    For unstructured ensemble, the minimum variable and check nodes are usually set to. The reason for this choice is out of the scope of this chapter.

  3. 3.

    The described protograph-based technique is not the only one to construct good QC-LDPC codes. Another possible approach is based on Euclidean and projective finite geometries [22, 23].

  4. 4.

    The words “horizontal” and “vertical” remind us that the check nodes and the variable nodes are associated with the rows and the columns of the parity-check matrix , respectively.

References

  1. T.M. Cover, J.A. Thomas, Elements of Information Theory (Wiley, 1991)

    Google Scholar 

  2. R.D. Fowler, L. Nordheim, Electron emission in intense electric fields. Proc. R. S. Lond. 119, 173–181 (1928)

    Article  ADS  Google Scholar 

  3. R. Micheloni, L. Crippa, A. Marelli (eds.), Inside NAND Flash Memories (Springer, 2010)

    Google Scholar 

  4. N. Mielke et al., Bit error rate in NAND Flash memories, in Proceedings of the 2008 IEEE International Symposium on Reliability Physics, Phoenix, AZ, USA, April/May 2008, pp. 9–19

    Google Scholar 

  5. J. Wang, T. Courtade, H. Shankar, R. Wesel, Soft information for LDPC decoding in flash: mutual-information optimized quantization, in Proceedings of the 2011 IEEE Global Telecommunication Conference, Houston, TX, USA, Dec 2011

    Google Scholar 

  6. S. Li, T. Zhang, Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding. IEEE Trans. VLSI 18, 1412–1420 (2010)

    Article  Google Scholar 

  7. R.G. Gallager, Low-Density Parity-Check Codes (MIT Press, Cambridge, Massachusetts, 1963)

    MATH  Google Scholar 

  8. C. Berrou, A. Glavieux, P. Thitimajshima, Near Shannon limit error-correcting coding and decoding: turbo-codes, in Proceedings of the 2003 International Symposium on Communication, vol. 2, May 1993, pp. 1064–1070

    Google Scholar 

  9. T. Richardson, R. Urbanke, The renaissance of Gallager’s low-density parity-check codes. IEEE Commun. Mag. 41, 126–131 (2003)

    Article  Google Scholar 

  10. N. Bonello, S. Chen, L. Hanzo, Low-density parity-check codes and their rateless relatives. IEEE Commun. Surv. Tutor. 13, 3–26 (2011)

    Article  Google Scholar 

  11. M. Tanner, A recursive approach to low complexity codes. IEEE Trans. Inf. Theory 27, 533–547 (1981)

    Article  MathSciNet  Google Scholar 

  12. M. Fossorier, Quasi-cyclic low-density parity-check codes from circulant permutation matrices. IEEE Trans. Inf. Theory 50, 1788–1793 (2004)

    Article  MathSciNet  Google Scholar 

  13. Z. Li, L. Chen, L. Zeng, S. Lin, W. Fong, Efficient encoding of low-density parity-check codes. IEEE Trans. Commun. 54, 71–81 (2006)

    Article  Google Scholar 

  14. M. Mansour, High-performance decoders for regular and irregular repeat-accumulate codes, in Proceedings of the IEEE 2004 IEEE Global Telecommunications Conference, Nov/Dec 2004, pp. 2583–2588

    Google Scholar 

  15. T. Richardson, M. Shokrollahi, R. Urbanke, Design of capacity-approaching irregular low-density parity-check codes. IEEE Trans. Inf. Theory 47, 619–637 (2001)

    Article  MathSciNet  Google Scholar 

  16. S.-Y. Chung, G.D. Forney Jr., T. Richardson, R. Urbanke, On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit. IEEE Commun. Lett. 5, 58–60 (2001)

    Article  Google Scholar 

  17. J. Thorpe, Low-density parity-check (LDPC) codes constructed from protographs, JPL INP, Technical Report, Aug 2003, pp. 42–154

    Google Scholar 

  18. J. Xu, L. Chen, L. Zeng, L. Lan, S. Lin, Construction of low-density parity-check codes by superposition. IEEE Trans. Commun. 53, 243–251 (2005)

    Article  Google Scholar 

  19. T. Richardson, R. Urbanke, The capacity of low-density parity-check codes under message-passing decoding. IEEE Trans. Inf. Theory 47, 599–618 (2001)

    Article  MathSciNet  Google Scholar 

  20. S. ten Brink, Convergence behavior of iteratively decoded parallel concatenated codes. IEEE Trans. Commun. 49, 1727–1737 (2001)

    Article  Google Scholar 

  21. G. Liva, M. Chiani, Protograph LDPC codes design based on EXIT analysis, in Proceedings of the 2007 IEEE Global Telecommunications Conference, Washington, DC, USA, Nov 2007, pp. 3250–3254

    Google Scholar 

  22. L. Chen, J. Xu, I. Djurdjevic, S. Lin, Near Shannon limit quasi cyclic low-density parity-check codes. IEEE Trans. Commun. 52, 1038–1042 (2004)

    Article  Google Scholar 

  23. H. Tang, J. Xu, Y. Kou, S. Lin, K. Abdel-Ghaffar, On algebraic construction of Gallager and circulant low density parity-check codes. IEEE Trans. Inf. Theory 50, 1269–1279 (2004)

    Article  MathSciNet  Google Scholar 

  24. M. Chiani, A. Ventura, Design and performance evaluation of some high-rate irregular low-density parity-check codes, in Proceedings of the 2001 Global Telecommunication Conference, San Antonio, TX, USA, Nov 2001, pp. 990–994

    Google Scholar 

  25. T. Richardson, Error floors of LDPC codes, in Proceedings of the 41st Annual Allerton Conference on Communication, Control and Computing (2003)

    Google Scholar 

  26. S. Abu-Surra, D. Divsalar, W.E. Ryan, Enumerators for protograph-based ensembles of LDPC and generalized LDPC codes. IEEE Trans. Inf. Theory 57, 858–886 (2011)

    Article  MathSciNet  Google Scholar 

  27. M. Flanagan, E. Paolini, M. Chiani, M. Fossorier, On the growth rate of the weight distribution of irregular doubly-generalized LDPC codes. IEEE Trans. Inf. Theory 57, 3721–3737 (2011)

    Article  MathSciNet  Google Scholar 

  28. D. Cavus, C. Haymes, Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets. IEEE Trans. Commun. 57, 1886–1888 (2009)

    Article  Google Scholar 

  29. L. Dolecek et al., Predicting error floors of structured LDPC codes: Deterministic bounds and estimates. IEEE J. Sel. Areas Commun. 27, 908–917 (2009)

    Article  Google Scholar 

  30. J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, X.-Y. Hu, Reduced-complexity decoding of LDPC codes. IEEE Trans. Commun. 53, 1288–1299 (2005)

    Article  Google Scholar 

  31. J. Zhao, F. Zarkeshvari, A. Banihashemi, On implementation of min-sum algorithm and its modifications for decoding low-density parity-check (LDPC) codes. IEEE Trans. Commun. 53, 549–554 (2005)

    Article  Google Scholar 

  32. J. Chen, M. Tanner, C. Jones, Y. Li, Improved min-sum decoding algorithms for irregular LDPC codes, in Proceedings of the 2005 IEEE International Symposium on Information Theory, Sept 2005, pp. 449–453

    Google Scholar 

  33. M. Davey, D. MacKay, Low-density parity check codes over GF(q). IEEE Commun. Lett. 2(6), 165–167 (1998)

    Article  Google Scholar 

  34. C. Poulliat, M. Fossorier, D. Declercq, Design of regular (2, dc) -LDPC codes over GF(q) using their binary images. IEEE Trans. Commun. 56(10), 1626–1635 (2008)

    Article  Google Scholar 

  35. G. Liva, E. Paolini, B. Matuz, S. Scalise, M. Chiani, Short turbo codes over high order fields. IEEE Trans. Commun. 61(6), 2201–2211 (2013)

    Article  Google Scholar 

  36. L. Dolecek, D. Divsalar, Y. Sun, B. Amiri, Non-binary protograph-based LDPC codes: enumerators, analysis, and designs. IEEE Trans. Inf. Theory 60(7), 3913–3941 (2014)

    Article  MathSciNet  Google Scholar 

  37. E. Paolini, M. Flanagan, Efficient and exact evaluation of the weight spectral shape and typical minimum distance of protograph LDPC Codes. IEEE Commun. Lett. 20(11), 2141–2144 (2016)

    Article  Google Scholar 

  38. X.-Y. Hu, M. Fossorier, E. Eleftheriou, On the computation of the minimum distance of low-density parity-check codes, in Proceedings of the 2004 International Conference on Communication, June 2004, pp. 767–771

    Google Scholar 

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Acknowledgements

The author wishes to thank R. Micheloni and A. Marelli for their careful proofcheck of this chapter.

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Authors and Affiliations

  1. DEI, University of Bologna, Bologna, Italy

    E. Paolini

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  1. E. Paolini
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Correspondence to E. Paolini .

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Editors and Affiliations

  1. Microsemi Corporation, Vimercate, Monza e Brianza, Italy

    Rino Micheloni

  2. Microsemi Corporation, Vimercate, Monza e Brianza, Italy

    Alessia Marelli

  3. Lightbits Labs, San Jose, California, USA

    Kam Eshghi

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Paolini, E. (2018). Low-Density Parity-Check (LDPC) Codes. In: Micheloni, R., Marelli, A., Eshghi, K. (eds) Inside Solid State Drives (SSDs). Springer Series in Advanced Microelectronics, vol 37. Springer, Singapore. https://doi.org/10.1007/978-981-13-0599-3_12

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