Design of 2-Bit Vedic Multiplier Using PTL and CMOS Logic

Abstract

The requirement of a high-speed multiplier is expanding. It is one of the most important hardware blocks in a processing system. A multiplier acts as a high delay block, and it also dissipates a lot of power. An ordinary processor requires more time and resources in multiplication operation. The proposed design of the 2-bit Vedic multiplier has been designed using pass transistor logic. The Vedic multiplier is the fastest, reliable, efficient, and low-power multipliers. By reducing the number of partial products, the delay also decreased and the system becomes faster. The design and the properties of this multiplier have been studied and performed using the Pyxis Schematic software (90 nm), and the power dissipation and delay have been compared with 2-bit multiplier using CMOS logic. The analysis is made for voltage range from 0.8 to 1.5 V.