Abstract
The motivation behind this paper is to give a full portrayal of a state-of-the-art SPI master/slave usage. Every single related issue, beginning from the elaboration of introductory details, till the last framework confirmation, is thoroughly examined and justified. In similarity with outline reuse approach, the concerned paper imparts high-grade intellectual properties i.e., IP’s that concerns in gathering all essential components that help in achieving presently required and modern ASIC or SoC applications using this SPI master and slave protocol. SPI is a standout among the most usually utilized serial interface protocols.
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Acknowledgements
The authors would like to thank the entire semiconductor team at CYIENT and the staff of KL University for their immense support and motivation in implementing this paper. Without their guidance, this paper would not have seen the light of the day.
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Yadlapati, A., Kakarla, H.K. (2018). Constrained Level Validation of Serial Peripheral Interface Protocol. In: Satapathy, S., Bhateja, V., Das, S. (eds) Smart Computing and Informatics . Smart Innovation, Systems and Technologies, vol 77. Springer, Singapore. https://doi.org/10.1007/978-981-10-5544-7_73
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DOI: https://doi.org/10.1007/978-981-10-5544-7_73
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