Skip to main content

Erweiterungen zur Höchstintegration

  • Chapter
  • First Online:
Silizium-Halbleitertechnologie
  • 6307 Accesses

Zusammenfassung

Verschiedene lokale Oxidationstechniken werden hinsichtlich der erreichbaren Planarität analysiert. Anschließend folgen die Integration von Spacer- und LDD-Strukturen zur Reduktion von Kurzkanaleffekten. Die Schaltungsintegration in SOI-Technik einschließlich der Substratherstellung wird vorgestellt. Nanometer-Transistoren und FINFET-Strukturen runden das Kapitel ab.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 29.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Literatur

  1. Ruge: Halbleiter-Technologie, Reihe Halbleiter-Elektronik, Bd. 4. Springer, Berlin (1984)

    Google Scholar 

  2. Isomae, S., Yamamoto, S., Aoki, S., Yajma, A.: Oxidation-induced stress in a LOCOS structure. IEEE Electron Device Lett. 7, 368–370 (1986)

    Article  Google Scholar 

  3. Kooi, E., van Lierop, J.G., Appels, J.A.: Formation of silicon nitride at a Si-SiO2 interface during local oxidation of silicon and during heat-treatment of oxidized silicon in NH3 gas. J. Electrochem. Soc. 123, 1117–1123 (1976)

    Article  Google Scholar 

  4. Sakuma, K., Arita, Y., Doken, M.: A new self-aligned planar oxidation technology. J. Electrochem. Soc. 134, 1503–1507 (1987)

    Article  Google Scholar 

  5. Hui, J.C., Chiu, T., Wong, S.S., Oldham, W.G.: Sealed interface local oxidation technology. IEEE Trans. Electron Devices. 29, 554–561 (1982)

    Article  Google Scholar 

  6. Chiu, K.Y., Moll, J.L., Manoliu, J.: A bird’s beak free local oxidation technology feasible for VLSI circuits fabrication. IEEE J. Solid State Circuits. 17, 166–170 (1982)

    Article  Google Scholar 

  7. ITRS: https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2015/0_2015%20ITRS%202.0%20Executive%20Report%20(1).pdf (2015). Zugegriffen am 01.07.2018

  8. Jackson, K.A.: Processing of semiconductors. In: Cahn, R.W., Haasen, P., Kramer, E.J. (Hrsg.) Materials Science and Technology, Bd. 16. VCH-Verlag, Weinheim (1996)

    Google Scholar 

  9. Imai, K., Unno, H.: FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI’s. IEEE Trans. Electron Devices. 31, 297–302 (1984)

    Article  Google Scholar 

  10. Tong, Q.-T., Gösele, U.: Semiconductor Wafer Bonding. Wiley, New York (1999)

    Google Scholar 

  11. Momose, H.S., Ono, M., Yoshitomi, T., Ohguro, T., Makamura, S., Saito, M., Iwai, H.: 1.5 nm direct-tunneling gate oxide Si MOSFET’s. IEEE Trans. Electron Devices. 43, 1233–1242 (1996)

    Article  Google Scholar 

  12. Robertson, J.: High Dielectric Constant Oxides. EDP Sciences, Cambridge (2004)

    Book  Google Scholar 

  13. Doering, R., Nishi, Y.: Semiconductor Manufacturing Technology. CRC Press LLC, Boca Raton (2008)

    Google Scholar 

  14. Engström, O., Raeissi, B., Hall, S., Buiu, O., Lemme, M.C., Gottlob, H.D.B., Hurley, P.K., Cherkaoui, K.: Navigation aids in the search for future high-k dielectrics: physical and electrical trends. Solid State Electron. 51, 622–626 (2007)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Fachmedien Wiesbaden GmbH, ein Teil von Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Hilleringmann, U. (2019). Erweiterungen zur Höchstintegration. In: Silizium-Halbleitertechnologie. Springer Vieweg, Wiesbaden. https://doi.org/10.1007/978-3-658-23444-7_11

Download citation

Publish with us

Policies and ethics