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FPGAs for High Accuracy Clock Synchronization over Ethernet Networks

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Field Programmable Logic and Application (FPL 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2778))

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Abstract

This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The network interface node on one hand provides all necessary hardware support to be flexibly used in a broad range of applications. The switch add-on on the other hand accounts for the packet delay uncertainties of Ethernet switches and is crucial for high accuracy clock synchronization.

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References

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Author information

Authors and Affiliations

  1. Institute of Computer Technology, ASIC Design, Vienna University of Technology, Viktor-Kaplan Straße 2, 2700, Wiener Neustadt, Austria

    Roland Höller

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  1. Roland Höller
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Editor information

Editors and Affiliations

  1. Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Road, SW7 2BT, London, UK

    Peter Y. K. Cheung

  2. Department of Electrical & Electronic Engineering, Imperial College London, Exhibition Road, SW7 2BT, London, UK

    George A. Constantinides

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© 2003 Springer-Verlag Berlin Heidelberg

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Höller, R. (2003). FPGAs for High Accuracy Clock Synchronization over Ethernet Networks. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_95

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  • DOI: https://doi.org/10.1007/978-3-540-45234-8_95

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40822-2

  • Online ISBN: 978-3-540-45234-8

  • eBook Packages: Springer Book Archive

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