Abstract
The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch level models.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Varghese, J., Butts, M., Batcheller, J.: An efficient logic emulation system. IEEE Trans. VLSI Syst. 1, 171–174 (1993)
Walters, S.: Computer-aided prototyping for ASIC-based system. IEEE Design Test Comput., 4–10 ( June 1991)
Khan, U.R., Owen, H.L., Hughes, J.L.: FPGA Architecture for ASIC Hardware Emulator. In: Proc. 6, IEEE ASIC Conference, p. 336 (1993)
Cheng, K.T., Huang, S.Y., Dai, W.J.: Fault Emulation: A New Methodology for Fault Grading. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 18(10), 1487–1495 (1999)
Dahlgren, P., Liden, P.: Efficient Modeling of Switch-Level Networks Containing Undetermined Logic Node States. In: Proc. IEEE/ACM Int. Conf. on CAD, pp. 746–752 (1993)
Bryant, R.E.: A Switch-Level Model and Simulator for MOS Digital Systems. IEEE Trans. Computers C-33(2), 160–177 (1984)
Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. IEEE Press, Los Alamitos (1995) (revised edition)
Verilog Hardware Descriptor Language Reference Manual (LRM) DRAFT. IEEE 1364 (April 1995)
Choi, G.S., Iyer, R.K.: FOCUS: An Experimental Environment for Fault Sensitivity Analysis. IEEE Trans. Computers 41(12), 1515–1526 (1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Miremadi, S.G., Ejlali, A. (2003). Switch Level Fault Emulation. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_82
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_82
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive