Abstract
In this paper, a modular reconfigurable architecture for efficient stuck-at fault simulation in digital circuits is described. The architecture is based on a Universal Faulty Gate Block, which models each 2-input gate by a 4-input Look-Up Table (LUT) and a Shift-Register (SR) with 3 stages, and relies on collapsing the stuck-at fault list of the gates using equivalence and dominance relations between faults. An example is presented, the expected performance is estimated and the applicability and limitations of the architecture are discussed.
This work was developed under the EC MEDEA+ A503 ASSOCIATE project, with funding from the Portuguese Government Agency "Agência de Inovação".
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Augusto, J.S., Almeida, C.B., Neto, H.C.C. (2003). A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_79
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DOI: https://doi.org/10.1007/978-3-540-45234-8_79
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