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Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2778))

Abstract

This paper describes how an FPGA based prototype environment aided the development of two multi-million gate ASICs: an IEEE 802.11 medium access controller and an IEEE 802.11a/b/g physical layer processor. Prototyping the ASICs on a reconfigurable platform enabled concurrent development by the hardware and software teams, and provided a high degree of confidence in the designs. The capabilities of modern FPGAs and their development tools allowed us to easily and quickly retarget the complex ASICs into FPGAs, enabling us to integrate the prototyping effort into our design flow from the start of the project. The effect was to accelerate the development cycle and generate an ASIC which had been through one pass of beta testing before tape-out.

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References

  1. The IEEE 802.11 Standards, http://grouper.ieee.org/groups/802/11/

  2. Ryan, P., et al.: A Single Chip COFDM Modem for IEEE 802.11a with Integrated ADCs and DACs. In: ISSCC 2001 (2001)

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© 2003 Springer-Verlag Berlin Heidelberg

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de Souza, L., Ryan, P., Crawford, J., Wong, K., Zyner, G., McDermott, T. (2003). Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_6

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  • DOI: https://doi.org/10.1007/978-3-540-45234-8_6

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40822-2

  • Online ISBN: 978-3-540-45234-8

  • eBook Packages: Springer Book Archive

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