Abstract
We show a systematic methodology to create DSP + field-programmable logic hybrid architectures by viewing it as a hardware/software codesign problem. This enables an embedded processor architect to evaluate the trade-offs in the increase in die area due to the field programmable logic and the resultant improvement in performance or code size. We demonstrate our methodology with the implementation of a Viterbi decoder. A key result of the paper is that the addition of a field-programmable data alignment unit (FPDAU) between the register-file and the computational blocks provides 15%-22% improvement in the performance of a Viterbi decoder on the state-of-the-art TigerSHARC DSP. The area overhead of the FPDAU is small relative to the DSP die size and does not require any changes to the programming model or the instruction set architecture.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Stitt, G., Vahid, F.: Energy Advantages of Microprocessor Platforms with On-chip Configurable Logic. IEEE Design and Test (2002)
Ye, Z., Moshovos, A., Hauck, S., Banerjee, P.: CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit. Computer Architecture News (2000)
Graham, P., Nelson, B.: Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. In: Lysaght, P., Irvine, J., Hartenstein, R.W. (eds.) FPL 1999. LNCS, vol. 1673, pp. 1–10. Springer, Heidelberg (1999)
Fisher, J., Faraboschi, P., Desoli, G.: Custom-Fit Processors: Letting Applications Define Architectures. Hewlett-Packard Laboratories Cambridge, Cambridge (1996)
Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software, http://www.ee.washington.edu/faculty/hauck/publications/ConfigCompute.pdf
Dehon, A.: The Density Advantage of Configurable Computing. IEEE Computer Magazine (2000)
Tessier, R., Burleson, R.: Reconfigurable Computing for Digital Signal Processing: A Survey. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (2001)
Hartenstein, R.: Reconfigurable Computing: A New Business Model – and it’s Impact on SoC Design. In: Proceedings Euromicro Symposium on Digital Systems Design, IEEE Comput. Soc., Los Alamitos (2001)
Ollmann, I.: Altivec, http://www.simdtech.org/apps/group_public/documents.php
Analog Devices: TigerSHARC DSP Hardware Specification, http://www.analog.com/Analog_Root/static/library/dspManuals/Tigersharc_hardware.html
Fridman, J.: Data Alignment for Sub-Word Parallelism in DSP. IEEE Signal Processing Magazine, IEEE, 27–35 (2000)
Texas Instruments: TMS320C6000 CPU and Instruction Set Reference Guide (2000), http://www-s.ti.com/sc/psheets/spru189f/spru189f.pdf
Razdan, R., Smith, M.: High-Performance Microarchitectures with Hardware- Programmable Functional Units. In: Proc. 27th Annual IEEE/ACM Intl. Symp. on Microarchitecture, pp. 172–180 (November 1994)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Oliver, J., Akella, V. (2003). Improving DSP Performance with a Small Amount of Field Programmable Logic. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_51
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_51
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive