Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics

Abstract

ASIC designs are becoming increasingly unaffordable due to rapidly increasing mask costs, greater manufacturing complexity, and the need for several re-spins to meet design constraints. Although FPGAs solve the NRE cost problem, they often fail to achieve the required performance and density. A Via-Patterned Gate Array (VPGA) that combines the regularity and design cost amortization benefits of FPGAs with silicon area and power consumption comparable to ASICs, was presented in [1]. The VPGA fabric consists of a regular interconnect architecture laid on top of an array of patternable logic blocks (PLBs). Customization of the logic and interconnect is done by the placement or removal of vias at a subset of the potential via locations. In this paper, we propose four heterogeneous PLBs for via-patterned fabrics and explore their performance, density and fabric utilization characteristics across several applications. Although this analysis is done in the context of the VPGA fabric, the proposed heterogeneous PLBs and the experimental methodology can be employed for any embedded programmable fabric.