Abstract
This paper introduces the ReSArT ( Reconfigurable Scalable Architecture Template). Based on a suitable design space model, ReSArT is parametrizable, scalable, and able to support all levels of parallelism. To derive architecture instances from the template, a design environment called DEfInE ( Design Environment for ReSArT Instance G eneration) is used, which integrates some existing academic and industrial tools with ReSArT-specific components, developed as a part of this work. Different architecture instances were tested with a set of 10 benchmark applications as a proof of concept, achieving a maximum degree of parallelism of 30 and an average degree of parallelism of nearly 20 16-bit operations per cycle.
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Sawitzki, S., Spallek, R.G. (2003). Architecture Template and Design Flow to Support Application Parallelism on Reconfigurable Platforms. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_134
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DOI: https://doi.org/10.1007/978-3-540-45234-8_134
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