Abstract
This chapter targets low-power techniques for nanopower SAR ADCs with reference voltage generation. First of all, a 106nW 10b 80 kS/s SAR ADC with duty-cycled reference generation is presented, where a CMOS voltage reference, a duty-cycling block, and a LDO are integrated with the SAR ADC together. Furthermore, a low-power bidirectional comparator is utilized in the SAR ADC to reduce the power consumption. The reference-included SAR ADC achieves a FoM of 2.4fJ/conv.-step. Second, an energy-free DAC reset technique, “swap-to-reset,” is presented to deal with the large DAC reset energy in a SAR ADC, which is usually large compared with DAC conversion energy. In the prototype, the DAC energy consumption is reduced by one-third with “swap-to-reset” applied to the 2 MSBs. Finally, a low-power and area-efficient discrete-time reference driver is introduced. By calculating the energy consumption of each switching step, the DAC in a SAR ADC can be driven by a pre-charged decoupling capacitor compensated by a small auxiliary DAC. In the prototype, the SNDR/SFDR are improved by 2.7 dB/11.6 dB after enabling the 3b DAC compensation and the discrete-time reference driver only adds 10.8% and 10.1% to the power and chip area of the SAR ADC, respectively.
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Liu, M., Pelzers, K., van Dommele, R., van Roermund, A., Harpe, P. (2019). Nanopower SAR ADCs with Reference Voltage Generation. In: Makinwa, K., Baschirotto, A., Harpe, P. (eds) Low-Power Analog Techniques, Sensors for Mobile Devices, and Energy Efficient Amplifiers . Springer, Cham. https://doi.org/10.1007/978-3-319-97870-3_4
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DOI: https://doi.org/10.1007/978-3-319-97870-3_4
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