Abstract
In this work, sub-threshold drain current model of Extended back Gate-Junctionless Transistor has been presented. Influence of fringing field from the gate over the extended source/drain region has also been included and verified with the ATLAS device simulation results. Superior gate controllability (compared to extended Source/drain conventional DG-JL transistor) and better device reliability (compared to schottky barrier source/drain DG-JL transistor) can be achieved using extended back gate in conventional DG-JL transistor. Device also shows superior Ion/Ioff ratio, sub-threshold slope, trans-conductance and device efficiency compared to conventional DG-JLT.
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References
D. Hisamoto et al., FinFET—a self-ali gned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)
J.-P. Colinge et al., Nanowire transistors without junctions. Nature Nanotechnol. 5(3), 225–229 (2010)
C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, J.-P. Colinge, Junctionless multigate field-effect transistor. Appl. Phys. Lett. 94(5), 053511–053512 (2009)
S. Sahay, M.J. Kumar, Symmetric operation in an extended back gate JLFET for scaling to the 5-nm regime considering quantum confinement effects. IEEE Trans. Electron Devices 64(1), 21–27 (2017)
J. Lee, H.E. Shin, Evanescent-mode analysis of short-channel effects in MOSFETs. J. of Korean Phys. Soc. 44(1), 50–55 (2004)
ATLAS User’s Manual: 3-D Device Simulator, SILVACO International, Version 5.14.0
V. Kumari, K. Sharmetha, M. Saxena, M. Gupta, Underlapped FinFET on insulator: Quasi 3D analytical model. Solid State Electron. 129, 138–149 (2017)
Acknowledgements
Abhineet Sharan (ENGS5560) would like to acknowledge Joint Science Academies Panel, Indian Academy of Sciences (IASc), Bangalore, India for selecting him under Science Academies’ Summer Research Fellowship Programme 2017.
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Kumari, V., Sharan, A., Saxena, M., Gupta, M. (2019). Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation. In: Sharma, R., Rawal, D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215. Springer, Cham. https://doi.org/10.1007/978-3-319-97604-4_98
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DOI: https://doi.org/10.1007/978-3-319-97604-4_98
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