Skip to main content

Sensing of Spintronic Memories

  • Chapter
  • First Online:
Book cover Sensing of Non-Volatile Memory Demystified

Abstract

Leakage power increase due to technology scaling has attracted a lot of attention to developing nonvolatile memory (NVM) technologies . Among the explored NVM candidates by the community, spintronic-based technologies such as magnetic RAM and spin-transfer torque RAM seem to be very promising. Conventionally, the main challenge of employing MRAMs as a possible candidate in universal memories is high power dissipation and long delay during write operation. However, in recent cutting-edge semiconductor technologies, the issue moves from write to read operation mainly due to significant suppression in read margin. Degradation in the read yield emerges from the increase in process variation and lowering of the supply voltage. Therefore, numerous research activities have been recently conducted to improve the read margin. This chapter reviews the sensing techniques, which have been developed to deal with the read margin degradation of MRAMs in scaled technology nodes. In addition, the chapter provides a background on different writing methods of MRAMs and possible solutions to improve the density of bit-cells.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 74.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.00
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 99.00
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Chau R, Doyle B, Datta S, Kavalieros J, Zhang K (2007) Integrated nanoelectronics for the future. Nature Mater 6(11):810–812

    Article  Google Scholar 

  2. Roy K, Mukhopadhyay S, Mahmoodi-Meimand H (2003) Leakage current mechanisms and leakage reduction techniques in deep submicrometer CMOS circuits. Proc IEEE 91(2):305–327

    Article  Google Scholar 

  3. Pal A (2014) Low-Power VLSI circuits and systems. Springer, New Delhi

    Google Scholar 

  4. Chen YH, Chan WM, Wu WC, Liao HJ, Pan KH, Liaw JJ, Chung TH, Li Q, Lin CY, Chiang MC, Wu SY, Chang J (2015) A 16 nm 128 Mb SRAM in high-k metal-gate finfet technology with write-assist circuitry for low-VMIN applications. IEEE J Solid-State Circuits 50(1):170–177

    Article  Google Scholar 

  5. Raychowdhury A, Geuskens B, Kulkarni J, Tschanz J, Bowman K, Karnik T, Lu SL, De V, Khellah MM (2010) PVT-and-aging adaptive word-line boosting for 8T SRAM power reduction. In: IEEE ISSCC Digest of Technical Papers, pp 352–353

    Google Scholar 

  6. Verma N, Chandrakasan A (2008) A 256 kb 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy. IEEE J Solid-State Circuits 43(1):141–149

    Article  Google Scholar 

  7. Hirabayashi O, Kawasumi A, Suzuki A, Takeyama Y, Kushida K, Sasaki T, Katayama A, Fukano G, Fujimura Y, Nakazato T, Shizuki Y, Kushiyama N, Yabe T (2009) A process-variation-tolerant dual-power-supply SRAM with 0.179 µm2 cell in 40 nm CMOS using level-programmable wordline driver. In: IEEE Int. Solid-State Circuits Conference on Digest of Technical Papers, pp 458–459

    Google Scholar 

  8. Nii K, Yabuuchi M, Tsukamoto Y, Ohbayashi S, Oda Y, Usui K, Kawamura T, Tsuboi N, Iwasaki T, Hashimoto K, Makino H, Shinohara H (2008) A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. In: VLSI Circuits Dig, pp 212–213

    Google Scholar 

  9. Ghanatian H, Hosseini SE, Zeinali B, Moradi F (2017) Quasi-Schottky-Barrier UTBB SOI MOSFET for low-power robust SRAMs. IEEE Trans Electron Devices 64(4):1575–1582

    Article  Google Scholar 

  10. Rim K, Chan K, Shi L, Boyd D, Ott J, Klymko N, Cardone F, Tai L, Koester S, Cobb M, Canaperi D, To B, Duch E, Babich I, Carruthers R, Saunders P, Walker G, Zhang Y, Steen M, Ieong M (2003) Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs. In: Int. Electron Device Meeting (IEDM) Technical Digest, pp 47–52

    Google Scholar 

  11. Wilk GD, Wallace RM, Anthony JM (2001) High-K gate dielectrics: current status and materials properties considerations. J Appl Phys 89(10):5243–5275

    Article  Google Scholar 

  12. Ota H, Hirano A, Watanabe Y, Yasuda N, Iwamoto K, Akiyama K, Okada K, Migita S, Nabatame S, Toriumi A (2007) Intrinsic origin of electron mobility reduction in high-K MOSFETs—from remote phonon to bottom interface dipole scattering. In: International Electron Device Meeting (IEDM) Technical Digest, pp 65–68

    Google Scholar 

  13. Frank DJ, Wong HSP (2000) Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs. Superlattices Microstruct 28(5–6):485–491

    Article  Google Scholar 

  14. Bagheriye L, Toofan S, Saeidi R, Zeinali B, Moradi F (2017) A reduced store/restore energy MRAM-Based SRAM cell for a non-volatile dynamically reconfigurable FPGA. In: IEEE transactions on circuits and systems II: Express briefs

    Google Scholar 

  15. Huai Y (2008) Spin-transfer torque MRAM (STT-MRAM): challenges and prospects. AAPPS Bull 18(6):33–40

    Google Scholar 

  16. Hosomi M, Yamagishi H, Yamamoto T, Bessho K, Higo Y, Yamane K, Yamada H, Shoji M, Hachino H, Fukumoto C, Nagao N, Kano H (2005) A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In: International Electron Device Meeting (IEDM) Technical Digest, pp 473–476

    Google Scholar 

  17. Mangin S, Ravelosona D, Katine JA, Carey MJ, Terris BD, Fullerton EE (2006) Current-induced magnetization reversal in nanopillars with perpendicular anisotropy. Nature Mater 5:210–215

    Article  Google Scholar 

  18. Meng H, Wang JP (2006) Spin transfer in nanomagnetic devices with perpendicular anisotropy. Appl Phys Lett 88:172506

    Google Scholar 

  19. Kishi T, Yoda H, Kai T, Nagase T, Kitagawa E, Yoshikawa M, Nishiyama K, Daibou T, Nagamine M, Amano M, Takahashi S, Nakayama M, Shimomura N, Aikawa H, Ikegawa S, Yuasa S, Yakushiji K, Kubota H, Fukushima A, Oogane M, Miyazaki T, Ando K (2008) Lower-current and fast switching of a perpendicular TMR for high speed and high density spin-transfer-torque MRAM. In: International Electron Device Meeting (IEDM) Technical Digest, pp 309–312

    Google Scholar 

  20. Nishimura N, Hirai T, Koganei A, Ikeda T, Okano K, Sekiguchi Y, Osada Y (2002) Magnetic tunnel junction device with perpendicular magnetization films for high-density magnetic random access memory. J Appl Phys 91(8):5246–5249

    Article  Google Scholar 

  21. Ohmori H, Hatori T, Nakagawa S (2008) Perpendicular magnetic tunnel junction with tunnelling magnetoresistance ratio of 64% using MgO(100) barrier layer prepared at room temperature. J Appl Phys 103:07A911

    Google Scholar 

  22. Yoshikawa M, Kitagawa E, Nagase T, Daibou T, Nagamine M, Nishiyama K, Kishi T, Yoda H (2008) Tunnel magnetoresistance over 100% in MgO-based magnetic tunnel junction films with perpendicular magnetic L10-FePt electrodes. IEEE Trans Magn 44(11):2573–2576

    Article  Google Scholar 

  23. Kim G, Sakuraba Y, Oogane M, Ando Y, Miyazaki T (2008) Tunnelling magnetoresistance of magnetic tunnel junctions using perpendicular magnetization L10-CoPt electrodes. Appl Phys Lett 92:172502

    Google Scholar 

  24. Carvello B, Ducruet C, Rodmacq B, Auffret S, Gautier E, Gaudin G, Dieny B (2008) Sizable room-temperature magnetoresistance in cobalt based magnetic tunnel junctions with out-of-plane anisotropy. Appl. Phys. Lett 92:102508

    Google Scholar 

  25. Park JH, Park C, Jeong T, Moneck MT, Nufer NT, Zhu JG (2008) Co/Pt multilayer based magnetic tunnel junctions using perpendicular magnetic anisotropy. J. Appl. Phys 103:07A917

    Google Scholar 

  26. Mizunuma K, Ikeda S, Park JH, Yamamoto H, Gan H, Miura K, Hasegawa H, Hayakawa J, Matsukura F, Ohno H (2009) MgO barrier-perpendicular magnetic tunnel junctions with CoFe/Pd multilayers and ferromagnetic insertion layers. Appl Phys Lett 95:232516

    Google Scholar 

  27. Ikeda S, Miura K, Yamamoto H, Mizunuma K, Gan HD, Endo M, Kanai S, Hayakawa J, Matsukura F, Ohno H (2010) A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction. Nature Mater 9:721–724

    Article  Google Scholar 

  28. Carpentieri M, Tomasello R, Ricci M, Burrascano P, Finocchio G. Micromagnetic study of electrical-field-assisted magnetization switching in MTJ devices. In: IEEE Transactions on Magnetics 50(11)

    Google Scholar 

  29. Fong X, Kim Y, Choday SH, Roy K (2014) Failure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM bit-cells. IEEE Trans Very Large Scale Integ Syst 22(2):384–395

    Google Scholar 

  30. Jovanovic B, Brum RM, Torres L (2015) Comparative analysis of MTJ/CMOS hybrid cells based on TAS and in-plane STT magnetic tunnel junctions. In: IEEE Transactions on Magnetics 51(2)

    Google Scholar 

  31. He W, Zhu T, Zhang XQ, Yang HT, Cheng ZH (2013) Ultrafast demagnetization enhancement in CoFeB/MgO/CoFeB magnetic tunneling junction driven by spin tunneling current. Sci Rep 3:2883

    Google Scholar 

  32. Farkhani H, Peiravi A, Moradi F (2016) Low-energy write operation for 1T-1MTJ STT-RAM bitcells with negative bitline technique. IEEE Trans Very Large Scale Integ (VLSI) Syst 24(4):1593–1597

    Google Scholar 

  33. Zheng T, Park J, Orshansky M, Erez M. Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring. In: Symposium on Low Power Electronics and Design, pp 229–234

    Google Scholar 

  34. Panagopoulos GD, Augustine C, Roy K (2013) Physics-based SPICE-compatible compact model for simulating hybrid MTJ/CMOS circuits. IEEE Trans Electron Devices 60(9):2808–2814

    Article  Google Scholar 

  35. Guo W, Prenat G, Javerliac V, El Baraji M, De Mestier D, Baraduc C, Dieny B (2010) SPICE modeling of magnetic tunnel junctions written by spin-transfer torque. J Appl Phys 43:215001

    Google Scholar 

  36. Madec M, Kammerer JB, Pregaldiny F, Herbrard L, Lallement C (2008) Compact modeling of magnetic tunnel junction. In: Proceedings on 6th International IEEE Northeast Workshop on Circuits System TAISA Conference, pp 229–232

    Google Scholar 

  37. Iga F, Yoshida Y, Ikeda S, Hanyu T, Ohno H, Endoh T (2012) Time-resolved switching characteristic in magnetic tunnel junction with spin transfer torque write scheme. Jpn J Appl Phys 51

    Google Scholar 

  38. Devolder T, Hayakawa J, Ito K, Takahashi H, Ikeda S, Crozat P, Zerounian N, Kim JV, Chappert C, Ohno H (2008) Single-shot time-resolved measurements of nanosecond-scale spin-transfer induced switching: stochastic versus deterministic aspects. Phys Rev Lett 100(5)

    Google Scholar 

  39. Farkhani H, Peiravi A, Madsen JK, Moradi F (2015) STT-RAM write energy consumption reduction by differential write termination method. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp 2936–2939

    Google Scholar 

  40. Farkhani H, Tohidi M, Peiravi A, Madsen JK, Moradi F (2017) STT-RAM energy reduction using self-referenced differential write termination technique. IEEE Trans Very Large Scale Integ (VLSI) Syst 25(2):476–487

    Google Scholar 

  41. Zeinali B, Karsinos D, Moradi F (2017) Progressive scaled STT-RAM for approximate computing in multimedia applications. IEEE Trans Circuits Syst II: Exp Briefs

    Google Scholar 

  42. Miron IM, Gaudin G, Auffret S, Rodmacq B, Schuhl A, Pizzini S, Vogel J, Gambardella P (2010) Current-driven spin torque induced by the Rashba effect in a ferromagnetic metal layer. Nature Mater 9:230–234

    Article  Google Scholar 

  43. Miron IM, Garello K, Gaudin G, Zermatten PJ, Costache MV, Auffret S, Bandiera S, Rodmacq B, Schuhl A, Gambardella P (2011) Perpendicular switching of a single ferromagnetic layer induced by in-plane current injection. Nature Lett 476:189–194

    Article  Google Scholar 

  44. Liu L, Lee OJ, Gudmundsen TJ, Ralph DC, Buhrman RA (2012) Current-induced switching of perpendicularly magnetized magnetic layers using spin torque from the spin Hall effect. Phys Rev Lett 109:096602

    Google Scholar 

  45. Liu L, Pai CF, Li Y, Tseng HW, Ralph DC, Buhrman RA (2012) Spin-torque switching with the giant spin Hall effect of tantalum. Science 336:555–558

    Article  Google Scholar 

  46. Pai CF, Liu L, Tseng HW, Ralph DC, Buhrman RA. Spin transfer torque devices utilizing the giant spin Hall effect of tungsten. Appl Phys Lett 101(12)

    Google Scholar 

  47. Dyakonov MI, Perel VI (1971) Current-induced spin orientation of electrons in semiconductors. Phys Lett A 35(6):459–460

    Article  Google Scholar 

  48. Hirsch JE (1999) Spin Hall effect. Phys Rev Lett 83(9)

    Google Scholar 

  49. Zhang S (2000) Spin Hall effect in the presence of spin diffusion. Phys Rev Lett 85(2):393–396

    Article  Google Scholar 

  50. Bychkov YA, Rashba EI (1984) Properties of a 2D electron gas with lifted spectral degeneracy. J Exp Theor Phys Lett 39(2):78–81

    Google Scholar 

  51. Yu G, Upadhyaya P, Fan Y, Alzate JG, Jiang W, Wong KL, Takei S, Bender SA, Chang LT, Jiang Y, Lang M, Tang J, Wang Y, Tserkovnyak Y, Amiri PK, Wang KL (2014) Switching of perpendicular magnetization by spin–orbit torques in the absence of external magnetic fields. Nature Nanotechnol 9:548–554

    Article  Google Scholar 

  52. Dyakonov MI, Perel VI (1971) Possibility of orienting electron spins with current. J Exp Theor Phys Lett 13(11):467–469

    Google Scholar 

  53. Jungwirth T, Wunderlich J, Olejník K (2012) Spin Hall effect devices. Nature Mater 11:382–389

    Article  Google Scholar 

  54. Zeinali B, Madsen JK, Raghavan P, Moradi F (2017) Ultra-Fast SOT-MRAM Cell with STT current for deterministic switching. In: IEEE International Conference on Computer Design (ICCD), pp 463–468

    Google Scholar 

  55. Wang Z, Zhao W, Deng E, Klein JO, Chappert C (2015) Perpendicular-anisotropy magnetic tunnel junction switched by spin Hall-assisted spin-transfer torque. J Phys D Appl Phys 48(6):065001

    Article  Google Scholar 

  56. Seo Y, Kwon KW, Roy K (2016) Area-efficient SOT-MRAM with a Schottky diode. IEEE Elect Dev Lett 37(8):982–985

    Article  Google Scholar 

  57. Kim Y, Fong X, Kwon KW, Chen MC, Roy K (2015) Multilevel spin-orbit torque MRAMs. IEEE Trans Elect Dev 62(2):561–568

    Article  Google Scholar 

  58. Seo Y, Fong X, Kwon KW, Roy K. Spin-Hall magnetic random-access memory with dual read/write ports for on-chip caches. IEEE Magn Lett 6

    Google Scholar 

  59. Zeinali B, Esmaeili M, Madsen JK, Moradi F (2017) Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications. In: 47th European Solid-State Device Research Conference (ESSDERC), pp 172–175

    Google Scholar 

  60. Ghosh S (2013) Design methodologies for high density domain wall memory. In: NANOARCH

    Google Scholar 

  61. Dong Q, Yang K, Fick L, Fick D, Blaauw D, Sylvester D. Low-power and compact analog-to-digital converter using spintronic racetrack memory devices. IEEE Trans Very Large Scale Integ (VLSI) Syst 25(3):907–918

    Google Scholar 

  62. Kim J, Na T, Kim JP, Kang SH, Jung SO (2014) A, split-path sensing circuit for spin torque transfer MRAM. IEEE Trans Circuits Syst-II Exp Briefs 61(3):193–197

    Article  Google Scholar 

  63. Na T, Kim JP, Kang SH, Jung SO (2016) Multiple-cell reference scheme for reduced reference resistance distribution in deep submicrometer STT-RAM. IEEE Trans Very Large Scale Integ (VLSI) Syst 24(9):2993–2997

    Google Scholar 

  64. Ono K, Kawahara T, Takemura R, Miura K, Yamamoto H, Yamanouchi M, Hayakawa J, Ito K, Takahashi H, Ikeda S, Hasegawa H, Matsuoka H, Ohno H (2009) A disturbance-free read scheme and a compact stochastic-spin-dynamics-based mtj circuit model for Gb-scale SPRAM. In: Proceedings of IEEE International Electron Devices Meeting, pp 1–4

    Google Scholar 

  65. Ren F, Park H, Dorrance R, Toriyama Y, Yang CKK. A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). In: Proceedings of 13th International Symposium Quality Electronic Design (ISQED’12), pp 275–282

    Google Scholar 

  66. Ren F, Park H, Yang CKK, Markovic D. Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs. IEEE Trans. Circuits Syst. I: Reg. Papers 60(11):2932–2939

    Google Scholar 

  67. Maffitt TM, DeBrosse JK, Gabric JA, Gow ET, Lamorey MC, Parenteau JS, Willmott DR, Wood MA, Gallagher WJ (2006) Design considerations for MRAM. IBM J Res Develop 50(1):25–49

    Article  Google Scholar 

  68. Jo K, Yoon H (2017) Variation-tolerant sensing circuit for ultralow-voltage operation of spin-torque transfer magnetic RAM. IEEE Trans Circuits Syst II: Exp Briefs 64(5):570–574

    Article  Google Scholar 

  69. Kang W, Pang T, Lv W, Zhao W. A dynamic dual-reference sensing scheme for deep submicrometer STT-MRAM. IEEE Trans Circuits Syst I: Reg Papers 64(1):122–132

    Google Scholar 

  70. Motaman S, Ghosh S, Kulkarni JP (2017) VFAB: A Novel 2-Stage STTRAM sensing using voltage feedback and boosting. IEEE Trans Circuits Syst I: Reg Papers

    Google Scholar 

  71. Javanifard J, Tanadi T, Giduturi H, Loe K, Melcher RL, Khabiri S, Hendrickson NT, Proescholdt AD, Ward DA, Taylor MA (2008) A 45 nm self-aligned-contact process 1 Gb NOR flash with 5 MB/s program speed. In: Proceeding of International Solid-State Circuits Conference, pp 424–426

    Google Scholar 

  72. Jefremow M, Kern T, Allers W, Peters C, Otterstedt J, Bahlous O, Hofmann K, Allinger R, Kassenetter S, Landsiedel DS (2013) Time-differential sense amplifier for sub-80 mV bitline voltage embedded STT-MRAM in 40 nm CMOS. In: Proceedings of International Solid-State Circuits Conference, pp 216–217

    Google Scholar 

  73. Song B, Na T, Kim J, Kim JP, Kang SH, Jung SO (2015) Latch offset cancellation sense amplifier for deep submicrometer STT-RAM. IEEE Trans. Circuits Syst. I: Reg. Papers 62(7):1776–1784

    Google Scholar 

  74. Na T, Kim J, Kim JP, Kang SH, Jung SO (2015) A double sensing-margin offset-canceling dual-stage sensing circuit for resistive nonvolatile memory. IEEE Trans Circuits Syst II: Exp Briefs 62(12):1109–1113

    Article  Google Scholar 

  75. Jeong G, Cho W, Ahn S, Jeong H, Koh G, Hwang Y, Kim K (2003) A 0.24-µm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme. IEEE J. Solid-State Circuits (JSSC) 38(11):1906–1910

    Google Scholar 

  76. Motaman S, Ghosh S, Kulkarni JP (2015) A novel slope detection technique for robust STTRAM sensing. In: IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp 7–12

    Google Scholar 

  77. Chen Y, Li H, Wang X, Zhu W, Xu W, Zhang T (2012) A 130 nm 1.2 V/3.3 V 16 Kb Spin-transfer torque random access memory with nondestructive self-reference sensing scheme. IEEE J Solid-State Circuits (JSSC) 47(2):560–573

    Google Scholar 

  78. Zeinali B, Madsen JK, Raghavan P, Moradi F. A novel nondestructive bit-line discharging scheme for deep submicrometer STT-RAM. IEEE Transactions on Emerging Topics in Computing

    Google Scholar 

  79. Toifl T, Menolfi C, Buchmann P, Kossel M, Morf T, Schmatz ML (2009) A 1.25–5 GHz clock generator with high-bandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS. IEEE J Solid-State Circuits (JSSC) 44(11):2901–2910

    Google Scholar 

  80. Phyu MW, Fu K, Goh WL, Yeo KS (2011) Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(1):1–9

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Farshad Moradi .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer International Publishing AG, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Zeinali, B., Moradi, F. (2019). Sensing of Spintronic Memories. In: Ghosh, S. (eds) Sensing of Non-Volatile Memory Demystified. Springer, Cham. https://doi.org/10.1007/978-3-319-97347-0_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-97347-0_1

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-97345-6

  • Online ISBN: 978-3-319-97347-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics