Abstract
The SSE floating-point instructions were introduced by Intel in 1998 and have continually expanded ever since. They operate on single-precision or double-precision data (Definition 5.3) residing in the 128-bit XMM registers or the 256-bit YMM registers. Some SSE instructions are packed, i.e., they partition their operands into several floating-point encodings to be processed in parallel; others are scalar, performing a single operation, usually on data residing in the low-order bits of their register arguments. The specifications presented in this chapter apply to both scalar and packed instructions that perform the operations of addition, multiplication, division, square root extraction, and FMA.
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Russinoff, D.M. (2019). SSE Floating-Point Instructions. In: Formal Verification of Floating-Point Hardware Design. Springer, Cham. https://doi.org/10.1007/978-3-319-95513-1_12
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DOI: https://doi.org/10.1007/978-3-319-95513-1_12
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