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Handbook of Signal Processing Systems pp 613–647Cite as

Hardware architectures for the fast Fourier transform

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Abstract

The fast Fourier transform (FFT) is a widely used algorithm in signal processing applications. FFT hardware architectures are designed to meet the requirements of the most demanding applications in terms of performance, circuit area, and/or power consumption. This chapter summarizes the research on FFT hardware architectures by presenting the FFT algorithms, the building blocks in FFT hardware architectures, the architectures themselves, and the bit reversal algorithm.

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Authors and Affiliations

  1. Linköping University, Linköping, Sweden

    Mario Garrido & Oscar Gustafsson

  2. Tampere University of Technology, Tampere, Finland

    Fahad Qureshi

  3. Department of Pervasive Computing, Tampere University of Technology, Tampere, Finland

    Jarmo Takala

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  1. Mario Garrido
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  2. Fahad Qureshi
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  3. Jarmo Takala
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  4. Oscar Gustafsson
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Correspondence to Fahad Qureshi .

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  1. Department of ECE and UMIACS, University of Maryland, College Park, MD, USA

    Shuvra S. Bhattacharyya

  2. Leiden Embedded Research Center, Leiden University Leiden Institute Advanced Computer Science, Leiden, The Netherlands

    Ed F. Deprettere

  3. RWTH Aachen University Software for Systems on Silicon, Aachen, Germany

    Rainer Leupers

  4. Department of Pervasive Computing, Tampere University of Technology, Tampere, Finland

    Jarmo Takala

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Garrido, M., Qureshi, F., Takala, J., Gustafsson, O. (2019). Hardware architectures for the fast Fourier transform. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-91734-4_17

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