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Flip-Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities

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Nanopackaging

Abstract

Semiconductor devices reached the nanoscale in the 2000s and have continued to shrink their features in accordance with Moore’s law. Semiconductor packaging, which is critical to ensure connectivity of these fine-featured semiconductor devices, has also kept pace with Moore’s law scaling to enable products to take advantage of the performance scaling opportunities afforded by silicon scaling. In doing so, packaging has been increasingly challenged to provide requisite interconnect scaling, form-factor scaling, process scaling, enhanced thermal management, improved signal integrity, improved power delivery, and adequate thermomechanical reliability in increasingly diverse applications. This chapter systematically examines the evolution, challenges, and opportunities of different aspects of flip-chip package scaling, typically used for high-performance silicon. Materials continue to play a critical role in the evolution of flip-chip packaging, and their influence and impact are also discussed to highlight their contributions and importance.

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Notes

  1. 1.

    Although there is a considerable amount of active research in non-solder-based area array interconnects, solder-based flip-chip interconnects are currently the most widely used die-to-die and die-to-package interconnects, for a variety of reasons including ease of manufacturing, interconnect compliance that reduces stress on the silicon backend layers, etc. In this chapter focus is restricted to packaging of nanoscale devices using solder-based flip-chip interconnects.

  2. 2.

    Focus on this chapter will be restricted to area array interconnects and will not cover wire-bonded interconnects in 3D die stacks.

  3. 3.

    Although the source is somewhat dated, it is the last time a formal pitch scaling target was published. As of 2017, the lowest pitch in commercially available stacked memories is 40 μm [11].

  4. 4.

    Thermal compression bonding (TCB) is the most common method of chip attach for fine-pitch die-die interconnects [13].

  5. 5.

    These processes are also referred to as No-Flow processes. The underfill and flux materials as integrated together and the underfill and chip attach processes are integrated as well [17].

  6. 6.

    Underfill CTE is modulated by filler content and tailored to minimize thermomechanical stresses.

  7. 7.

    The cored package technology is described here as a superset of substrate technologies. In recent years, there has been considerable focus on developing thin coreless package substrate technologies that essentially consist only of the dielectric layers [24] and wafer-level fan-out technologies that use wafer-level patterning processes to enable interconnect scaling [25].

  8. 8.

    Large packages used in high-performance products use pitches in the 1.00 mm range to pitches in the 0.8 mm range, while smaller packages used in handheld devices have seen pitches as low as 0.4 mm.

  9. 9.

    Management of thermal transients is also an important consideration during testing of semiconductor devices and when they are expected to operate in burst modes; however this is beyond the scope of this chapter.

  10. 10.

    In addition to particle-filled polymers listed, solders are also used as TIM materials. Solders have significantly higher bulk thermal conductivity (30–50 W/(m-°K)) compared to filled polymers (~3 W/(m-°K)); however they require very different and potentially expensive processing conditions.

Abbreviations

BGA:

Ball Grid Array

BOM:

Bill of Materials

BPA:

Bisphenol-A

BW:

Bandwidth

C4:

Controlled Collapse Chip Connection

CG:

Coarse-grained

CNT:

Carbon Nanotube

CPI:

Chip Package Interactions

CPU:

Central Processing Unit

CSAM:

C-Mode (Confocal) Scanning Acoustic Microscopy

CSP:

Chip Scale Package

CTE:

Coefficient of Thermal Expansion

CVFF:

Consistent Valence Force Field

DEM:

Discrete Element Model

DFT:

Density Functional Theory

DIP:

Dual Inline Package

DPD:

Dissipative Particle Dynamics

DRAM:

Dynamic Random Access Memory

EM:

Electromagnetic

EMC:

Epoxy Molding Compound

EMIB:

Embedded Multi-Die Interconnect Bridge

EPN:

Epoxy Phenol Novolac

FCBGA:

Flip Chip Ball Grid Array

FCC:

Face-centered cubic

FCIP:

Flip Chip in Package

FCLGA:

Flip Chip Land Grid Array

FCPGA:

Flip Chip Pin Grid Array

FET:

Field Effect Transistor

FIVR:

Fully Integrated Voltage Regulator

FLI:

First Level Interconnect

FOPLP:

Fan-Out Panel Level Package

FOWLP:

Fan-Out Wafer Level Package

GPU:

Graphics Processing Unit

HMC:

Hybrid Memory Cube

HSIO:

High Speed Input/Output

HVM:

High Volume Manufacturing

IC:

Integrated Circuit

IHS:

Integrated Heat Spreader

ILD:

Inner Layer Dielectric

I/O:

Input/Output

IOT:

Internet of Things

KGD:

Known Good Die

LGA:

Land Grid Array

LJ:

Lennard-Jones

LQFP:

Low-profile Quad Flat Package

MBVR:

Mother Board Voltage Regulator

MCP:

Multi-Chip Package

MD:

molecular dynamics

MM:

molecular mechanics

MMAP:

Molded Matrix Array Package

MOSFET:

Metal-Oxide-Semiconductor FET

NEMD:

Non-Equilibrium Molecular Dynamics

NPU:

Network Processing Unit

NPT:

Isothermal-isobaric ensemble (conservation of substance amount N, pressure P and temperature T)

NVT:

canonical ensemble (conservation of substance amount N, volume V and temperature T)

PBC:

Periodic Boundary Conditions

PBGA:

Plastic Ball GA

PCB:

Printed Circuit Board

PCFF:

Polymer Consistent Force Field

PDN:

Power Delivery Network

PGA:

Pin Grid Array

PoP:

Package on Package

PTH:

Plated Through Hole

QFJ:

Quad Flat J-Leaded Package

QFN:

Quad Flat Package No Lead

QFP:

Quad Flat Package

RC:

Resistance x Capacitance (time constant)

RDL:

Redistribution Layer

RF:

Radio Frequency

RH:

Relative Humidity

RT:

Room Temperature

SAC:

Tin-Silver-Copper (Sn-Ag-Cu)

SAP:

Semi-Additive Process

SCSP:

Stacked die Chip Scale Package

SI:

Signal Integrity

SiP:

System in a Package

SLI:

Second Level Interconnect

SoC:

System on a Chip

SOJ:

Small Outline J-Leaded Package

SOP:

Small Outline Package

SRAM:

Static Random Access Memory

SSOP:

Shrink Small Outline Package

TCB:

Thermo-Compression Bonding

TCP:

Tape Carrier Package

TDP:

Thermal Design Power

Tg:

Glass Transition Temperature

TIM:

Thermal Interface Material

TQFP:

Thin Quad Flat Package

TSOP:

Thin Small Outline Package

TSV:

Through Silicon Via

UBM:

Under Bump Metallization

VdW:

Van der Waals

VHR:

Voltage Holding Ratio

VR:

Voltage Regulator

WLCSP:

Wafer Level Chip Scale Package

WLP:

Wafer Level Package

ZIP:

Zig-Zag Inline Package

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Acknowledgments

The authors would like to thank Brent Stone and Donald Tran from Intel Corporation for their help in providing background information on socket technologies. We would also like to thank Chris Matayabas and Gaurang Choksi for reviewing the chapter and providing guidance on enhancing the chapter.

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Authors and Affiliations

  1. Intel Corporation, Chandler, AZ, USA

    Debendra Mallik, Ravi Mahajan, Kaladhar Radhakrishnan, Kemal Aygun & Bob Sankman

  2. Tectus Corporation, Saratoga, CA, USA

    Nachiket Raravikar

Authors
  1. Debendra Mallik
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  2. Ravi Mahajan
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  3. Nachiket Raravikar
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  4. Kaladhar Radhakrishnan
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  5. Kemal Aygun
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Corresponding author

Correspondence to Ravi Mahajan .

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Editors and Affiliations

  1. Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA

    James E. Morris

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Mallik, D., Mahajan, R., Raravikar, N., Radhakrishnan, K., Aygun, K., Sankman, B. (2018). Flip-Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities. In: Morris, J. (eds) Nanopackaging. Springer, Cham. https://doi.org/10.1007/978-3-319-90362-0_31

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