Abstract
The development of the IC package is a dynamic technology. Applications that were unattainable only a decade ago are now commonplace thanks to advances in package design. Moreover, the increasing demand for smaller, faster and cheaper products is forcing the packaging technology to keep pace with the progress in semiconductor technology.
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Notes
- 1.
Note: Not every reader has access to the published articles of microelectronic conferences and magazines. A lot of effort has therefore been given to refer to those publications that are directly accessible through web pages on the Internet. However, these data may be volatile because some owners update and change the contents on their web pages, so that some of the references below may only be accessible during a short time after the print of this book. Finally a lot more information on the various subjects can be found by searching the Web with the right entry, which can be easily extracted from the corresponding subject. Good Luck!
References
Note: Not every reader has access to the published articles of microelectronic conferences and magazines. A lot of effort has therefore been given to refer to those publications that are directly accessible through web pages on the Internet. However, these data may be volatile because some owners update and change the contents on their web pages, so that some of the references below may only be accessible during a short time after the print of this book. Finally a lot more information on the various subjects can be found by searching the Web with the right entry, which can be easily extracted from the corresponding subject. Good Luck!
JEDEC, Joint Electron Devices Engineering Councils, <www.jedec.org>
OKI Semiconductor, “Package Information 5. Thermal-Resistance of IC Package”, <www.ti.com/lit/an/spra953c/spra953c.pdf>
G.Q. Zhang, et al., “Mechanics of Microelectronics”, Springer 2006, <www.springer.com>
Kevin J. Hess et al., “Reliability of Bond Over Active Pad Structures for 0.13-μm CMOS Technology”, <www.freescale.com/files/technology_manufacturing/doc/ECTC_2003_BOND_OVER_ACTIVE_KH.pdf>
Elpida Completes Development of Cu-TSV (Through Silicon Via) Multi-Layer 8-Gigabit DRAM”, <www.elpida.com/en/news/2009/08-27.html>
Rao R. Tummala, “Moore's Law Meets Its Match”, IEEE Spectrum, June 2006, pp. 38–43, <http://spectrum.ieee.org/computing/hardware/moores-law-meets-its-match/0>
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Veendrick, H. (2019). Packaging. In: Bits on Chips. Springer, Cham. https://doi.org/10.1007/978-3-319-76096-4_14
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DOI: https://doi.org/10.1007/978-3-319-76096-4_14
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