Abstract
RISC-V is an open ISA that has been calling the attention worldwide by its fast growth and adoption. It is already supported by GCC, Clang and the Linux Kernel. However, none of the currently available RISC-V emulators are capable of providing good, near-native, emulation performance. Thus, in this work, we investigate if faster emulators for RISC-V could be created. Since Dynamic Binary Translation (DBT) is the most common, and fastest, technique to implement emulators, we focus our investigation on the quality of the translated code, arguably the most important source of overhead when emulating code with DBT. To this end, we implemented and evaluated a LLVM-based Static Binary Translation (SBT) engine to investigate whether or not it is possible to produce high-quality translations from RISC-V to x86 and ARM. We explored different translation techniques and managed to design an SBT engine that produces translated code that is only 1.2x/1.3x slower than native x86/ARM code, which supports the claim that it is possible to build near-native RISC-V emulators for x86 and ARM hosts. We also analyze the main sources of overheads, compare the code produced by our SBT against the code produced by a popular DBT and provide insights on the potential performance impact of the proposed techniques on DBTs.
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Acknowledgments
We would like to thank CNPq (Grant #: 313012/2017-2), CAPES (PROCAD 2966/2014), and the São Paulo Research Foundation, FAPESP (Grant #: 2013/08293-7) for supporting this research.
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Lupori, L., do Rosario, V.M., Borin, E. (2020). High-Performance RISC-V Emulation. In: Bianchini, C., Osthoff, C., Souza, P., Ferreira, R. (eds) High Performance Computing Systems. WSCAD 2018. Communications in Computer and Information Science, vol 1171. Springer, Cham. https://doi.org/10.1007/978-3-030-41050-6_9
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DOI: https://doi.org/10.1007/978-3-030-41050-6_9
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