Abstract
We discuss the fabrication technologies for IC chips in this chapter. We will focus on the main process steps and especially on those aspects that are of particular importance for understanding how they affect, and in some cases drive, the layout of ICs. All our analyses in this chapter will be for silicon as the base material; the principles and understanding gained can be applied to other substrates as well. Following a brief introduction to the fundamentals of IC fabrication (Sect. 2.1) and the base material used in it, namely silicon (Sect. 2.2), we discuss the photolithography process deployed for all structuring work in Sect. 2.3. We will then present in Sect. 2.4 some theoretical opening remarks on typical phenomena encountered in IC fabrication. Knowledge of these phenomena is very useful for understanding the process steps we cover in Sects. 2.5–2.8. We examine a simple exemplar process in Sect. 2.9 and observe how a field-effect transistor (FET) – the most important device in modern integrated circuits—is created. To drive the key points home, we provide a review of each topic at the end of every section from the point of view of layout design by discussing relevant physical design aspects.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
One electron absorbs a kinetic energy of 1 eV along a potential gradient of 1 V.
- 2.
Named after Polish scientist Jan Czochralski, who invented the method in 1915 while investigating the crystallization rates of metals.
- 3.
To expose a 200 mm wafer with a 5X-photomask in only one step, the mask diameter would have to be 1 m. The same applies to the optics required. Photomasks and optical devices of these sizes are non-viable from both a technical and commercial perspective.
- 4.
These fillets have a positive electrical effect because the local field strength increases at the outer corners are capped. The same applies to current density increases at inside radiuses of bent interconnects.
- 5.
The etching rate R is the thickness T of the material being etched per unit time t, i.e., R = T/t.
- 6.
Layers that define the doped areas have always been known historically as “diffusion layers” among academics and in industry, even though the substrates are doped by implantation. We wish to dispense with this deceptive term in this book by calling these layers “doping layers”.
- 7.
- 8.
The Bipolar-CMOS-DMOS (BCD) process technology is typically used to make products where high power or voltage must be controlled by a digital controller. BCD technology incorporates analog components (Bipolar, CMOS), digital components (CMOS) and high-voltage transistors (DMOS) on the same die (Chap. 1, Sect. 1.2.2).
- 9.
The term “Damascening” refers a historical metalworking artistic practice, in which different metals such as gold or silver are interlayed into a darkly oxidized steel background, to produce intricate designs and patterns.
- 10.
The “yield” is the ratio of the number of functioning chips to the total number of fabricated chips.
- 11.
Strictly speaking, the relationship only applies at thermodynamic equilibrium, i.e., when the generation and recombination of charge carriers are in equilibrium, which is what we assume here.
- 12.
p-doped substrates are favored over n-doped substrates, as the die substrate is then at the lowest potential in the integrated circuit. If we define this potential as the reference potential (0 V), all our calculations will be based on positive voltages.
- 13.
A thin oxide, which deflects the ions and therefore prevents a parallel impact, is applied on top of the wafer surface.
References
R.J. Baker, CMOS: Circuit Design, Layout, and Simulation (Wiley, 2010). ISBN 978-0-470-88132-3, 2010
A. Hastings, The Art of Analog Layout, 2nd edn. (Pearson, 2005). ISBN 978-0131464100
O. Kononchuk, B.-Y. Nguyen, Silicon-On-Insulator (SOI) Technology: Manufacture and Applications (Woodhead Publishing Series in Electronic and Optical Materials, Vol. 58) (Woodland Publishing, 2014). ISBN 978-0857095268
J. Lienig, M. Thiele, Fundamentals of Electromigration-Aware Integrated Circuit Design (Springer, 2018), ISBN 978-3-319-73557-3. https://doi.org/10.1007/978-3-319-73558-0
J.D. Plummer, M. Deal, P.D. Griffin, Silicon VLSI Technology: Fundamentals, Practice, and Modeling (Pearson, 2000). ISBN 978-0130850379
P. van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing (McGraw-Hill Publ. Comp., 2004). ISBN 978-0071432412
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Lienig, J., Scheible, J. (2020). Technology Know-How: From Silicon to Devices. In: Fundamentals of Layout Design for Electronic Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-39284-0_2
Download citation
DOI: https://doi.org/10.1007/978-3-030-39284-0_2
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-39283-3
Online ISBN: 978-3-030-39284-0
eBook Packages: EngineeringEngineering (R0)