Abstract
This chapter introduces clock network reconfiguration for wide adaptation from nominal voltage down to deep sub-threshold voltages. Reconfiguration resolves the conflicting repeater insertion requirements at different voltages, in conventional static clock networks. In reconfigurable clock networks, the number of repeater levels is dynamically adapted to the supply voltage to ultimately mitigate the clock skew degradation across a wide voltage range. At nominal voltage, the number of repeater levels is adjusted to the highest value to mitigate the important clock skew contribution of wire delays. At lower voltages, the number of repeaters is progressively lowered to mitigate the increasingly dominant clock skew contribution of repeaters.
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Notes
- 1.
The cost of hold fix is determined by several factors such as type and number of critical paths and flip-flops, the clock network size, the nominal skew target.
- 2.
This can be done in either manual or automatic CTS mode in commercial tools. In manual CTS mode, this is achieved by explicitly specifying the number and the type of clock repeaters at each level. In auto CTS mode, the level-balanced option needs to be enabled in the clock specification file (e.g., add “LevelBalanced YES” in the .ctstch file in Cadence PnR tools).
- 3.
The same consideration holds for any other logic gate in the clock path, such as clock gaters. In this case, the presence of clock gaters in selected clock paths was balanced in other paths by adding a dummy clock gater in the same clock network level, to preserve the same number of logic gates across all clock paths.
References
L. Lin, S. Jain, M. Alioto, Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage, in IEEE ISSCC Digest of Technical Papers, San Francisco (CA), (2017), pp. 440–441
L. Lin, S. Jain, M. Alioto, Reconfigurable clock networks for wide voltage scaling. IEEE J. Solid State Circuits 54(9), 2622–2631 (2019)
M. Alioto (ed.), Enabling the Internet of Things—From Integrated Circuits to Integrated Systems (Springer, Berlin, 2017)
T. Xanthopoulos (Ed.), Clocking in Modern VLSI Systems, 2009.
M. Alioto, E. Consoli, G. Palumbo, Flip-Flop Design in Nanometer CMOS—From High Speed to Low Energy (Springer, Berlin, 2015)
T. Burd, T. Pering, A. Stratakos, R. Brodersen, A dynamic voltage scaled microprocessor system, in IEEE ISSCC Digest of Technical Papers, (2000)
S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan, A. Kumar, S. Kumar, R. Ramanarayanan, V. Erraguntla, J. Howard, S. Vangal, S. Dighe, G. Ruhl, P. Aseron, H. Wilson, N. Borkar, V. De, S. Borkar, A 280 mV-to-1.2 V wide-Operating-range IA-32 processor in 32 nm CMOS, in IEEE ISSCC Digest of Technical Papers, San Francisco (CA), (2012)
W. Wang, P. Mishra, System-wide leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in multitasking systems. IEEE Trans. VLSI Syst. 20(5) (2012)
A.P. Chandrakasan, D.C. Daly, D.F. Finchelstein, J. Kwong, Y.K. Ramadass, M.E. Sinangil, V. Sze, N. Verma, Technologies for ultradynamic voltage scaling. Proc. IEEE 98(2), 191–214 (2010)
M. Seok, D. Jeon, C. Chakrabati, D. Blaauw, D. Sylvester, Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs, in Proceedings of ICICDT, Austin (TX), (2012)
D. Jacquet, F. Hasbani, P. Flatresse, R. Wilson, F. Arnaud, G. Cesana, T.D. Gilio, C. Lecocq, T. Roy, A. Chhabra, C. Grover, O. Minez, J. Uginet, G. Durieu, C. Adobati, D. Casalotto, F. Nyer, P. Menut, A. Cathelin, I. Vongsavady, P. Magarshack, A 3 GHz dual core processor ARM Cortex TM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization. IEEE J. Solid State Circuits 49(4), 812–826 (2014)
F. Abouzeid, S. Clerc, B. Pelloux-Prayer, F. Argoud, P. Roche, 28 nm CMOS, energy efficient and variability tolerant, 350 mV-to-1.0 V, 10 MHz/700 MHz, 252 bits Frame Error-Decoder, in Proceedings of ESSCIRC, (2012), pp. 153–156
S. Hsu, A. Agarwal, M. Anders, S. Mathew, H. Kaul, F. Sheikh, R. Krishnamurthy, A 280 mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm CMOS, in IEEE ISSCC Digest of Technical Papers, San Francisco (CA), (2012)
M. Seok, D. Blaauw, D. Sylvester, Robust clock network design methodology for ultra-low voltage operations. IEEE J. Emerg. Select. Topics Circuits Syst. 1(2), 120–130 (2011)
J.R. Tolbert, X. Zhao, S.K. Lim, S. Mukhopadhyay, Analysis and design of energy and slew aware subthreshold clock systems. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 30(9), 1349–1358 (2011)
X. Zhao, J.R. Tolbert, S. Mukhopadhyay, S.K. Lim, Variation-aware clock network design methodology for ultralow voltage (ULV) Circuits. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 31(8), 1222–1234 (2012)
C. Sitik, W. Liu, B. Taskin, E. Salman, Design methodology for voltage-scaled clock distribution networks. IEEE Trans. VLSI Syst. 24(10), 3080–3093 (2016)
S. Kim, M. Seok, Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems, in Proceedings of ISLPED 2014, La Jolla (CA), (2014), pp. 99–104
J. Wang, N. Pinckney, D. Blaauw, D. Sylvester, Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect, in 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen (China), (2015), pp. 1–4
M. Alioto, G. Scotti, A. Trifiletti, A novel framework to estimate the path delay variability on the back of an envelope via the Fan-Out-of-4 Metric. IEEE Trans. CAS Pt. I 64(8), 2073–2085 (2017)
C. Augustine, C. Tokunaga, A. Malavasi, A. Raychowdhury, M. Khellah, J. Tschanz, V. De, Characterization of PVT variation & aging induced hold time margins of flip-flop arrays at NTV in 22nm tri-gate CMOS, in Proceedings of IEDM, (2016), pp. 894–897
S. Jain, L. Lin, M. Alioto, Dynamically adaptable pipeline for energy-efficient microarchitectures under wide voltage scaling. IEEE J. Solid State Circuits 53(2), 632–641 (2018)
D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw, D. Sylvester, A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS. IEEE J. Solid State Circuits 47(1) (2012)
S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K.K. Das, W. Haensch, E.J. Nowak, D.M. Sylvester, Ultralow-voltage, minimum-energy CMOS. IBM J. Res. Dev. 50(4/5) (2006)
D. Bol, J.D. Vos, C. Hocquet, F. Botman, F. Durvaus, S. Boyd, D. Flandre, J. Legat, SleepWalker: A 25-MHz 0.4-V Sub-mm2 7uW/MHz Microcontroller in 65-nm LP/GP CMOS for low-carbon wireless sensor nodes. IEEE J. Solid State Circuits 48(1), 20–32 (2013)
J. Myers, A. Savanth, R. Gaddh, D. Howard, P. Prabhat, D. Flynn, A subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN applications with 14 power domains, 10T SRAM, and integrated voltage regulator. IEEE J. Solid State Circuits 51(1), 31–44 (2016)
C. Tokunaga, J. F. Ryan, C. Augustine, J. P. Kulkarni, Y. Shih, S. T. Kim, R. Jain, K. Bowman, A. Raychowdhury, M. M. Khellah, J. W. Tschanz, V. De, "A Graphics Execution Core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep," in IEEE ISSCC Digest of Technical Papers, San Francisco (CA), 2014, pp. 108-109.
M. Keating, D. Flynn, A. Gibbons, R. Aitken, K. Shi, Low Power Methodology Manual For System-on-Chip Design (Springer, Berlin, 2007)
M. Alioto, Ultra-low power VLSI circuit design demystified and explained: a tutorial. IEEE Trans. Circuits Syst. Pt. I 59(1), 3–29 (2012)
M. Alioto, G. Palumbo, M. Pennisi, Understanding the effect of process variations on the delay of static and domino logic. IEEE Trans. VLSI Syst. 18(5), 697–710 (2010)
M. Eisele, J. Berthold, D. Schmitt-Landsiedel, R. Mahnkopf, The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans. VLSI Syst. 5(4), 360–368 (1997)
K. Bowman, S. Duvall, J. Meindl, Impact of Die-to-Die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits 37(2), 183–190 (2002)
N. Nedovic, W.W. Walker, V.G. Oklobdzija, A test circuit for measurement of clocked storage element characteristics. IEEE J. Solid State Circuits 39(8), 1294–1304 (2004)
T.E. Rahkonen, J.T. Kostamovaara, The use of stabilized CMOS delay lines for the digitization of short time intervals. IEEE J. Solid State Circuits 28(8), 887–894 (1993)
P. Dudek, S. Szczepanski, J.V. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J. Solid State Circuits 35(2), 240–247 (2000)
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Jain, S., Lin, L., Alioto, M. (2020). Reconfigurable Clock Networks, Automated Design Flows, Run-Time Optimization, and Case Study. In: Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling. Springer, Cham. https://doi.org/10.1007/978-3-030-38796-9_5
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