Skip to main content
SpringerLink
Log in

Modern Code Applied in Stencil in Edge Detection of an Image for Architecture Intel Xeon Phi KNL

  • Conference paper
  • First Online:
Technologies and Innovation (CITI 2019)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1124))

Included in the following conference series:

Abstract

Modern, high-performance computers are built with a combination of heterogeneous resources, including multi-core and many cores processors, large cache, fast memory, mesh communication between large processes bandwidth, as well as high support for Input/Output capabilities. In order to achieve the best hardware results it is necessary to design highly-performance parallel software with faster modern code that could take full advantage of the vast amount of resources of today’s modern machines. Code modernization encompasses a wide range of activities that aim to improve the performance of highly parallel software. Code modernization is an issue that is being discussed more and more in the field of parallel software development.

In this context, the experimentation with Stencil codes through a series of strategies for reorganizing code and algorithms, has shown to increase thread parallelism, vector/SIMD operations and compute intensity in modern architectures.

For example, with the use of Stencil codes we have achieved a better performance in image edge detection by a factor of three faster than we could achieved with a standard processor.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Andreolli, C., Thierry, P., Borges, L., Skinner, G., Yount, C.: Characterization and optimization methodology applied to stencil computations. In: Reinders, J., Jeffers, J. (eds.) High Performance Parallelism Pearls: Multicore and Many-Core Programming Approaches, vol. 1, pp. 377–396. Morgan Kaufmann, Boston, MA, USA (2015). https://doi.org/10.1016/B978-0-12-802118-7.00023-6. http://www.sciencedirect.com/science/article/pii/B9780128021187000236

    Chapter  Google Scholar 

  2. Cebrián, J.M., Cecilia, J.M., Hernández, M., García, J.M.: Code modernization strategies to 3-D stencil-based applications on Intel Xeon Phi: KNC and KNL. Comput. Math. Appl. 74(10), 2557–2571 (2017)

    Article  MathSciNet  Google Scholar 

  3. Chandra, R.: Parallel Programming in OpenMP. Morgan Kaufmann, Burlington (2001)

    Google Scholar 

  4. Cramer, T., Schmidl, D., Klemm, M., an Mey, D.: OpenMP programming on Intel ® Xeon Phi \({\text{TM}}\) coprocessors: an early performance comparison. In: Proceedings Many Core Applications Research Community (MARC) Symposium, pp. 38–44 (2012)

    Google Scholar 

  5. Datta, K., Kamil, S., Williams, S., Oliker, L., Shalf, J., Yelick, K.: Optimization and performance modeling of stencil computations on modern microprocessors. SIAM Rev. 51(1), 129–159 (2009). https://doi.org/10.1137/070693199. http://epubs.siam.org/doi/abs/10.1137/070693199

    Article  MATH  Google Scholar 

  6. Datta, K., et al.: Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures. In: Proceedings of the ACM/IEEE Conference on Supercomputing, SC 2008, p. 4 (2008). http://dl.acm.org/citation.cfm?id=1413370.1413375

  7. Dursun, H., et al.: A multilevel parallelization framework for high-order stencil computations. In: Sips, H., Epema, D., Lin, H.-X. (eds.) Euro-Par 2009. LNCS, vol. 5704, pp. 642–653. Springer, Heidelberg (2009). https://doi.org/10.1007/978-3-642-03869-3_61

    Chapter  Google Scholar 

  8. Henretty, T., Veras, R., Franchetti, F., Pouchet, L.N., Ramanujam, J., Sadayappan, P.: A stencil compiler for short-vector SIMD architectures. In: Proceedings of the 27th International ACM Conference on Supercomputing, pp. 13–24. ACM (2013). https://doi.org/10.1145/2464996.2467268. http://doi.acm.org/10.1145/2464996.2467268

  9. Hernández, M., Cebrián, J.M., Cecilia, J.M., García, J.M.: Evaluation of 3-D stencil codes on the Intel Xeon Phi coprocessor. In: Parallel Computing (ParCo) 2015, Edimburgo, Reino Unido, September 2015. http://www.ditec.um.es/~jmgarcia/papers/parco-2015.pdf

  10. Jeffers, J., Reinders, J.: Intel Xeon Phi Coprocessor High Performance Programming. Morgan Kaufmann Publishers Inc., Boston (2013)

    Google Scholar 

  11. Kamil, S., Datta, K., Williams, S., Oliker, L., Shalf, J., Yelick, K.: Implicit and explicit optimizations for stencil computations. In: Proceedings of the Workshop on Memory System Performance and Correctness, MSPC 2006, pp. 51–60. ACM, New York, USA (2006). https://doi.org/10.1145/1178597.1178605. http://doi.acm.org/10.1145/1178597.1178605

  12. Kamil, S., Husbands, P., Oliker, L., Shalf, J., Yelick, K.: Impact of modern memory subsystems on cache optimizations for stencil computations. In: Proceedings of the 2005 Workshop on Memory System Performance, MSP 2005, pp. 36–43. ACM, New York, NY, USA (2005). https://doi.org/10.1145/1111583.1111589. http://doi.acm.org/10.1145/1111583.1111589

  13. Krishnamoorthy, S., Baskaran, M., Bondhugula, U., Ramanujam, J., Rountev, A., Sadayappan, P.: Effective automatic parallelization of stencil computations. In: Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2007, pp. 235–244. ACM, New York, USA (2007). https://doi.org/10.1145/1250734.1250761. http://doi.acm.org/10.1145/1250734.1250761

  14. McCool, M., Robison, A.D., Reinders, J.: Stencil and recurrence. In: Structured Parallel Programming: Patterns for Efficient Computation, pp. 199–207. Morgan Kaufmann Publishers Inc., Boston, MA, USA (2012). https://doi.org/10.1016/B978-0-12-415993-8.00007-4. http://www.sciencedirect.com/science/article/pii/B9780124159938000074

    Chapter  Google Scholar 

  15. MPI: The Message Passing Interface (MPI) standard, 23 May 2019. http://www.mcs.anl.gov/research/projects/mpi/

  16. OpenMP: OpenMP Architecture Review Board: The OpenMP Specification, 23 May 2019. http://www.openmp.org/

  17. Pearce, M.: What is code modernization? (2015). https://software.intel.com/en-us/articles/what-is-code-modernization

  18. Rahman, R.: Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers, 1st edn. Apress, Berkely (2013)

    Book  Google Scholar 

  19. Rahman, S.M.F., Yi, Q., Qasem, A.: Understanding stencil code performance on multicore architectures. In: Proceedings of the 8th ACM International Conference on Computing Frontiers, CF 2011, pp. 30:1–30:10. ACM, New York, NY, USA (2011). https://doi.org/10.1145/2016604.2016641. http://doi.acm.org/10.1145/2016604.2016641

  20. Reinders, J., Jeffers, J. (eds.): High Performance Parallelism Pearls: Multicore and Many-Core Programming Approaches, vol. 2, 1st edn. Morgan Kaufmann Publishers Inc., Boston (2015)

    Google Scholar 

  21. Reinders, J., Jeffers, J.: Characterization and auto-tuning of 3DFD. In: High Performance Parallelism Pearls, Multicore and Many-Core Programming Approaches, pp. 377–396. Morgan Kaufmann (2014)

    Google Scholar 

  22. Rosales, C., et al.: KNL utilization guidelines. Technical report, TR-16-03, Texas Advanced Computing Center, The University (2016)

    Google Scholar 

  23. Seaton, M., Mason, L., Matveev, Z.A., Blair-Chappell, S.: Vectorization advice. In: Reinders, J., Jeffers, J. (eds.) High Performance Parallelism Pearls Volume Two: Multicore and Many-Core Programming Approaches, vol. 2, pp. 441–462. Morgan Kaufmann, Boston, MA, USA (2015). https://doi.org/10.1016/B978-0-12-803819-2.00015-X. http://www.sciencedirect.com/science/article/pii/B978012803819200015X

    Chapter  Google Scholar 

  24. Strzodka, R., Shaheen, M., Pajak, D., Pomeranian, W.: Impact of system and cache bandwidth on stencil computations across multiple processor generations. In: Proceedings of the Workshop on Applications for Multi-and Many-Core Processors (A4MMC) at ISCA (2011)

    Google Scholar 

  25. Tang, Y., Chowdhury, R.A., Kuszmaul, B.C., Luk, C.K., Leiserson, C.E.: The pochoir stencil compiler. In: Proceedings of the Twenty-Third Annual ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 2011, pp. 117–128. ACM, New York, NY, USA (2011). https://doi.org/10.1145/1989493.1989508. http://doi.acm.org/10.1145/1989493.1989508

  26. Trottenberg, U., Oosterlee, C.W., Schuller, A.: Multigrid. Academic Press, Cambridge (2000)

    MATH  Google Scholar 

  27. Vladimirov, A., Asai, R., Karpusenko, V. (eds.): Parallel Programming and Optimization with Intel Xeon Phi Coprocessors, vol. 1, 2nd edn. Colfax International, CA, USA (2015)

    Google Scholar 

Download references

Acknowledgments

Authors are grateful to Autonomous University of Guerrero (UAGro) and TecNM/Technological Institute of Chilpancingo for supporting this work.

Author information

Authors and Affiliations

  1. Engineering Faculty, Autonomous University of Guerrero, Chilpancingo, México

    Mario Hernández-Hernández & Edilia Rodríguez Maldonado

  2. TecNM/Technological Institute of Chilpancingo, Chilpancingo, Mexico

    José Luis Hernández-Hernández

  3. Government and Public Management Faculty, Autonomous University of Guerrero, Chilpancingo, México

    Israel Herrera Miranda

Authors
  1. Mario Hernández-Hernández
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. José Luis Hernández-Hernández
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Edilia Rodríguez Maldonado
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Israel Herrera Miranda
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Mario Hernández-Hernández .

Editor information

Editors and Affiliations

  1. Universidad de Murcia, Murcia, Spain

    Rafael Valencia-García

  2. Universidad de Castilla la Mancha, Toledo, Spain

    Gema Alcaraz-Mármol

  3. Universidad Agraria del Ecuador, Guayaquil, Ecuador

    Javier Del Cioppo-Morstadt

  4. Universidad Agraria del Ecuador, Guayaquil, Ecuador

    Néstor Vera-Lucio

  5. Universidad Agraria del Ecuador, Guayaquil, Ecuador

    Martha Bucaram-Leverone

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Hernández-Hernández, M., Hernández-Hernández, J.L., Maldonado, E.R., Miranda, I.H. (2019). Modern Code Applied in Stencil in Edge Detection of an Image for Architecture Intel Xeon Phi KNL. In: Valencia-García, R., Alcaraz-Mármol, G., Del Cioppo-Morstadt, J., Vera-Lucio, N., Bucaram-Leverone, M. (eds) Technologies and Innovation. CITI 2019. Communications in Computer and Information Science, vol 1124. Springer, Cham. https://doi.org/10.1007/978-3-030-34989-9_12

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-34989-9_12

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-34988-2

  • Online ISBN: 978-3-030-34989-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation