Fast Fault Simulation for Detecting Erroneous Connections in ICs

Abstract

Imperfections in manufacturing processes can be modelled as unwanted connections (defects, or faults) that are added to the nominal, "golden", fault-free design of an electronic circuit to study their impact. Testing in a structured way using fault simulation techniques to obtain information on the impact of faults and guaranteeing defect coverage and test quality is not a common practice during the design of analog or mixed signal ICs. Fault simulation involves defect extraction and injection of defects into the netlist of the analog or mixed signal circuit and performing analogue simulation (DC, AC, or Transient) of the tests. The major drawback is the long CPU time associated with the many analogue simulations. For example, if simulation of the test suite takes one hour, it may take several years to perform all simulations for more than 10,000 defects (when not exploiting parallelism).

In the transient simulation the solution due to an inserted fault is compared to a golden, fault-free, solution. A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We obtain a significant speed-up of over 100x over sequentional approaches, while a useful estimate of the detection status and the defect coverage can still be ensured. Our strategy can also be used when exploiting parallelism.