Abstract
With the advancement in the VLSI technology, the demand for low power consumption and high performance increased gradually. When the applications of data retention are considered, then the need for advanced memory units is taken into account. This requirement of enhanced memory units is incorporated with the concept of conservation of energy which is achieved by using low-power techniques. In digital circuits, flip-flops are the essential memory and timing elements. New methods and techniques needed to be developed for implementing energy-efficient low-power flip flops. This paper proposes dual edge-triggered flip-flop (DETFF) along with gating technique, one of the most reliable low-power techniques which provide one-time solution to low-power applications. The DETFF circuit based on gating technique is simulated using MENTOR GRAPHICS tool in 180 nm technology. This design is efficient in reducing power dissipation leading to the reduction in area and delay and subsequently leads to the high speed of the device.
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The authors would like to thank CDAC, Noida, IP University for their support and constant motivation for the successful completion of this work and providing a platform to enhance our skills and practical implementation of this research work.
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Mall, A., Khanna, S., Noor, A. (2020). Design of Low-Power Dual Edge-Triggered Retention Flip-Flop for IoT Devices. In: Singh, P., Kar, A., Singh, Y., Kolekar, M., Tanwar, S. (eds) Proceedings of ICRIC 2019 . Lecture Notes in Electrical Engineering, vol 597. Springer, Cham. https://doi.org/10.1007/978-3-030-29407-6_60
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DOI: https://doi.org/10.1007/978-3-030-29407-6_60
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